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Speculation: Ryzen 3000 series

For Matisse that seems to be the case. Either there is a small iGPU on the IO die or there's some other reason why the IO die is the size it is. Well, it depends on whatever that IO die has a small iGPU or not. AMD wanted to cut some rumors about GPU chiplet for the near future. So Matisse...
- Zapetu
- Post #1,039
- Jan 12, 2019
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

I have been very busy lately and it's nice that chiakokhua beat me to it with his illustrations. :) At some point I will also have mine out. There might still be some server only logic in the Rome IO die that can be removed from the Matisse IO die, but sure, it would still be a very little...
- Zapetu
- Post #1,037
- Jan 12, 2019
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

Cache coherency logic is split between different infinity fabric nodes. Here's a pretty good illustration of the Raven Ridge SoC and different Infinity Fabric nodes. There's a cache-coherent master for the CCX and two masters for the GPU. There's also a cache-coherent slave for each memory...
- Zapetu
- Post #929
- Jan 10, 2019
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

This is still just speculation but if they're using the same organic package (edit: or at least the same basic layout, why would they otherwise put that one chiplet in the corner) for all AM4 SKUs (they could alternatively have different packages for different chiplet configurations) then all...
- Zapetu
- Post #922
- Jan 9, 2019
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

To be fair, I think it's just a typo and it should have been 32 (or 24) PCI-E lanes. Personally I have to say that everything makes a lot more sense now than it did when we were talking about half SoC's with DDR4 MCs and IO splitted between dies or many other bifurcated variations. It was still...
- Zapetu
- Post #917
- Jan 9, 2019
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

He said all a long to take it with a pinch of salt and that it was all rumors, leaks and speculation. He also said in his video that the latest rumors were dropped on him on email and he choose to believe them. His previous speculation about chiplets and IO dies has been very interesting and...
- Zapetu
- Post #858
- Jan 9, 2019
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

While most of you have already found this, I will post this for those few that haven't spotted this live stream yet: It should start about in half an hour. Let's hope for some concrete information about 7nm products.
- Zapetu
- Post #798
- Jan 9, 2019
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

AdoredTV posted a new video on what we should expect from CES 2019: He still stands by his leak that Ryzen 3000 CPU's (desktop, 7nm, 6-16 cores, AM4) will be announced at CES 2019. The highest end 16 core SKU and all G variants with Navi graphics would be announced later. Previous leaks also...
- Zapetu
- Post #487
- Dec 31, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

TSMC 7nm using cobalt for contacts is exactly what raghu78 assumed two weeks ago. So that article is just confirming what Scotten Jones meant by "TSMC 7nm adds cobalt". To say the least, it looks very promising for Zen2 clock speeds.
- Zapetu
- Post #486
- Dec 31, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

Since raghu78 should not self-promote his Twitter account, I will do it for him :) (even though I don't have any connections to him or to chiakokhua for that matter):
- Zapetu
- Post #325
- Dec 15, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

At this point I was asking if you really thought that the current Rome chiplet (72mm²) has enough room for all the IO required for a full SoC comparable to current Ryzen models. Then you clarified that you meant that each Rome chiplet might have enough room for half the IO. I still think...
- Zapetu
- Post #324
- Dec 15, 2018
- Forum: CPUs and Overclocking
[Anandtech] Intel's Architecture Day 2018

There's a really interesting interview with David Kanter (from realworldtech.com) on Gamer's Nexus Youtube channel related to this thread: I'm adding it here since someone in here might not have yet seen it. I'm currently watching it myself. Addition: David Kanter talks in the interview...
- Zapetu
- Post #12
- Dec 13, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

Ok, here's an illustration of the speculative 1xDDR4 and half the IO per die design (based on what moinmoin and dnavas suggested): As you can see there would likely be the following core configurations: Ryzen 3 (6C): (3 + 3) + (0 + 0), 1Ch DDR4 Ryzen 5 (8C): (2 + 2) + (2 + 2), 2Ch DDR4 Ryzen...
- Zapetu
- Post #315
- Dec 13, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

As I undestood it, there is no IO die, just two equal sized CPU dies containing half of the IO both. There's only one IF-link between them so that's one IF hop. And that's basically all it is. 6C model would only have one (single channel) DDR4 controller while other models would have two. I'm...
- Zapetu
- Post #312
- Dec 13, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

That's exactly right. It would cost much less for them to differentiate their products using different 14nm IO dies (i.e. main dies) than having many different 7nm designs. Also 7nm would be best utilized having large caches and tightly packed cores (execution units) rather than more IO that...
- Zapetu
- Post #310
- Dec 13, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

I read your post and it's certainly possible to do but would still require a new 7nm die (as you said) likely just used for desktop products. Also it's a ccNUMA design but you are right that about half of the time you would use the local memory controller. And if you optimize for it, you could...
- Zapetu
- Post #308
- Dec 13, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

Violently arguing may be a little bit of an exaggeration but it's always a good thing to have many points of view. ;) I have to say that AdoredTV is deep down a very genuine guy and he will always try to correct his mistakes in his latest videos and takes constructive criticism seriously. He...
- Zapetu
- Post #303
- Dec 13, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

That wasn't the point. If you would get a Rome CPU on your hands with no previous knowledge what it contains, you could guess that the IO die is using a different process than the smaller dies but just by looking at it, you have no way to know for sure. You could make educated guesses based on...
- Zapetu
- Post #298
- Dec 13, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

The whole point of the chiplet design was to be highly versatile. That would mean that a 72nm² chiplet would only contain features that are needed for all use cases including 8 cores, 32MB L3 cache and an IF link to connect to an IO die (or some other (main) die). We have already calculated that...
- Zapetu
- Post #294
- Dec 13, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

Thats's also what I thought. If the consoles would not use a monolithic die or a separate 14nm IO die then sure using one standard Rome CPU chiplet and a larger Navi part with GDDR6 controllers on die would be a good choice. That would allow AMD to use those avarage or below avarage Rome...
- Zapetu
- Post #290
- Dec 13, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

What about 6C models then? Would they have just one DDR4 IMC or would they have two dies each? That would be a lot of 7nm silicon for a $100 SKU even if most of it would be salvaged dies. They would also have to separate dual DD4 memory controllers which they haven't done previously (sure their...
- Zapetu
- Post #288
- Dec 13, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

It's adds some latency for sure but we can't really state that it would kill gaming performance. There's likely 32MB of L3 cache for each chiplet and that would certainly benefit games. Zen 2 also has better prefetchers and that also helps to feed the cores regardless of what design they chose...
- Zapetu
- Post #286
- Dec 13, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

The problem here is not whatever it's feasible to cut the IO die in parts but what AdoredTV is suggesting at 4.08 in his newest video. That doesn't leave any room for any 14nm silicon. Still we should not take these leaks and rumors as facts and hopefully by CES 2019 we are much wiser. So we...
- Zapetu
- Post #285
- Dec 13, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

Rome I/O die (~420mm²) already has (improved?) DDR4 PHYs, PCIe 4.0, and other IO that could be used for a smaller 14nm IO die. Only in the case that Rome IO die would use 14HP instead of 14LPP, it would make things much more complicated. Current Zeppelin and Raven Ridge also has a lot of...
- Zapetu
- Post #284
- Dec 13, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

If we're assuming that there actually is a Navi GPU chiplet (or Navi main die) then there would be (at least) two possible designs (keeping all previous recent assumptions): With a small ~72mm² Navi-chiplet With a larger (~120 mm²) Navi GPU die Both designs have pros and cons but both would...
- Zapetu
- Post #277
- Dec 12, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

I made some comparisons for Summit/Pinnacle Ridge and Raven Ridge using Die Per Wafer Calculator. I used otherwise the same parameters as before but for 14nm I assumed defect density of 0.08 #/mm² and low $3000 cost per wafer as AdoredTV did here. This is nothing new and if you have the time, I...
- Zapetu
- Post #275
- Dec 12, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

Let's try to analyze what AdoredTV actually said in his latest video especially starting at 3.22. As far as I understood, AdoredTV still believes that there will be models from 6C up to 16C so let's go with that. His source mentions "chiplets" (all on 7nm) so it doesn't seem to be just a...
- Zapetu
- Post #272
- Dec 12, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

I agree. Maybe in 2020-2022 AMD will realease some APU with one stack of HBM3/4 cache. For now it's just Kaby Lake G. HBM1 stack (5.48 mm × 7.29 mm = 39.95 mm²) had much smaller size than HBM2 stack (7.75 mm × 11.87 mm = 91.99 mm²) that is over twice as large...
- Zapetu
- Post #203
- Dec 7, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

While AMD has stated that ThreadRippers use chips from the top binned 5% , we don't know what the portion of the top binned chips for EPYCs is. So while your calculations are otherwise correct, we don't know if that 5% stands for EPYCs also. I'll admit that I should not have put that 5% there...
- Zapetu
- Post #200
- Dec 7, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

That's exactly right. EPYCs (low leakage, high perf/W) come mostly from different bin than TRs (high leakage, high clockspeeds) . There are some (low volume) exceptions and likely Rome will have similar SKUs (16C or 32C). Still it's important to be aware that the top 5% bin of chips for...
- Zapetu
- Post #196
- Dec 7, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

Here's some rumors that Next Gen Xbox will feature Zen2 and AMD next-gen GPU: https://wccftech.com/xbox-scarlett-4k-60fps/ It's based on a video made by Brad Sams: I didn't see this posted in here yet. Take it as you will. It doesn't really say anything about chiplets, just that both next...
- Zapetu
- Post #159
- Dec 6, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

True, the chiplet design is a big change and will have both benefits and some disadvantages. But if AMD has chosen this path for desktop also then I'm sure that overall advantages are much greater than (some minor) drawbacks. People at AMD know x86 market very well and don't make hasty or...
- Zapetu
- Post #144
- Dec 6, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

Please note that not all EPYCs will be 64 core versions with 8 chiplets, only some of them will be that. There will likely be EPYC SKUs with 4 chiplets or even less, we don't know what the requirements for the IO die are and what configurations are supported. It may even be that all...
- Zapetu
- Post #141
- Dec 6, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

AdoredTV has talked about this in many of his videos and while he doesn't always get everything right (nobody does), I think he has a very good and valid point about chiplets and speed binning. Only the top 5% (*) (high leakage, high clocking) or so will be EPYCs and ThreadRippers and another...
- Zapetu
- Post #138
- Dec 6, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

Don't you mean with low TDPs? You can always undervolt your CPU. I am a bit of ecomaniac (mayte that's a little bit of an overstatement) an eco frriendly person myself and I do care about the enviroment, climat change and such things and I think that Lisa Su mentioned somewhere that one of the...
- Zapetu
- Post #124
- Dec 5, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

Sorry that I misunderstood you. Sure, 8C or even 6C would be enough for mainstream desktop for a while. Still 12C for AM4 would be quite attractive if you do any kind of rendering /video editing or similar kind of work and don't want to spend all that money that HEDT platforms (like...
- Zapetu
- Post #122
- Dec 5, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

I hope they have. I agree that any kind of iGPU would be a benefit for Ryzen Pro or even any kind of non-gaming focused desktop platform. For many non "tech-savvy" users it might be too much of an hassle to buy a discrete GPU. Well, most of them would buy so called market PCs anyway. But Rome...
- Zapetu
- Post #120
- Dec 5, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

Navi 20CU chiplet seems like an overkill for office PCs for sure. But it will likely possibly be memory started anyway but still two ~72nm² 7nm chiplets seems like a lot. But as itsmydamnation pointed out, manufacturing costs per chiplet aren't really that high (about $17 per chiplet). It's like...
- Zapetu
- Post #117
- Dec 5, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

So even if 7nm is about 50-70% (Edit: fixed from 60% to 70%) more expensive to manufacture (per absolute die size), the cost per transistor, or whatever is the right measurement called, would still be much lower. As far as I know, we have talked about about 2x density improvements. So likely PS5...
- Zapetu
- Post #113
- Dec 5, 2018
- Forum: CPUs and Overclocking
Speculation: Ryzen 3000 series

I had to admit that It does sound too good to be true, I'll give you that. 6C/12T would have one salvaged 6C/8C chiplet (72mm² 7nm), one dummy chiplet and one IO die (maybe about 100mm² 12/14nm). Do we even know what manufacturing costs for that would be? I think we tend to overestimate many...
- Zapetu
- Post #107
- Dec 5, 2018
- Forum: CPUs and Overclocking

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