I think that the topic of the impact of cache and delays on IPC has been developed so much that it is obvious. Let's go ahead and continue the topic of Zen5.
A processor with a 0.2 ms latch can process more instructions per cycle than a processor with a 0.3 ms latch.
Less downtime means the core can accept more instructions (data) and process more of them at the same time.
This is an increase in the number of instructions processed per cycle, or...
Core architecture changes + unified L3 cache as a whole architecture. I don't know how you can still think that L3 was completely irrelevant to IPC.
Not true. If core A 4GHz + VCache compared to core B 4GHz without VCache allows you to get +15% more FPS, this is an increase in the IPC of the...
RaptorLake has no inter-chiplet latency problem and the RAM controller is on the same chip. Thanks to 2MB L2 instead of 1.25MB, RaptorLake gains approximately +4-5% higher IPC.
Zen has a RAM controller on a separate IOD, so it needs larger L3 to compensate, and this is mainly why it benefits...
V Cache is a lot of additional billions of transistors to obtain additional IPC layers from the cores. VCache only allows you to get close to the theoretical peak IPC of a given architecture. To see further gains again, you need a new and more complex core design (to put it very simply).
Everything matters. Games benefit mainly from this.
Just a moment ago you said that you don't see the difference, that each core has direct access to the common L3 of 32MB instead of 16MB and at the same time inter-core communication benefits because it does not have to communicate in the same...
And did I write somewhere that there are no other improvements apart from the cache?
VCache clearly shows that reducing latency in accessing RAM by using it less frequently results in additional IPC gain, which is mainly used by games.
I see this is still a problem.
CCD Zen 2 has 2x CCX(4 cores and 16MB)
(2x 16 MB (total 32 MB)).
The problem is that each Zen2 core only has direct access to 16MB, and another 16MB is connected by a much slower IF.
CCD Zen3 has 1x CCX, i.e. 8 cores and 32MB. This allows each Zen3 core to have...
At what point am I wrong? Enlighten me.
Sorry. My fault. I took this post in the wrong context.
The topic is mainly addressed to the previous speaker who pretends to be an expert and still does not see that the transition from Zen 2 to Zen 3 increases direct access from 16MB to 32MB for each...
You clearly wanted to deny that cache has any effect on IPC, since AMD didn't state that on the slide. While claiming that delays have no impact on IPC.
You were both wrong.
Are you sure it didn't increase L3? Each Zen3 core has direct access to 32 MB instead of just 16 MB like a single Zen2 core. I see the difference, but you don't see it.
Obfuscation? Read previous entries. Previous speakers claim that cache has nothing to do with the increase in IPC. I have provided clear proof that it is quite the opposite and the proof is VCache which can increase a lot of IPC. Not in every application, but the L3 design itself and its...
Why would they add HT to Core 2 when it already provided a large (compared to Core 1) IPC increase, even a gigantic one compared to P4(Netbrust). HT has been added to the expanded and redesigned Nehalem. This was the plan and bargaining chip of the new LGA1366 platform.
C&C:
"VCache provides a notable 33% L3 hitrate increase here. Bringing average hitrate to 78% is more than enough to compensate for the slight L3 latency increase. GHPC enjoys a 9.67% IPC gain from running on the VCache CCD, so the other CCD should fall short even with its higher clock speed."...
It is largely Front-End and Load Store.
I don't know how else to explain it.
If the cache had nothing to do with IPC, the 3DV cache would provide absolutely nothing. And yet he can give a specific boost.
The biggest problem with Zen2 was the division into 2 CCXs, which made communication at...
C&C you will also read about solutions advertised by AMD that are presented as unique but in fact are not.
Latency reduction is part of measurable IPC because it causes the core logic to wait less for data and can therefore execute more instructions at the same time.
The division on the slide is of a marketing nature and is not very insightful. It doesn't take cache into account at all because specific parts of the core are responsible for retrieving data.
The truth is that the cache and RAM of the controller are part of the measurable IPC. By subtracting...
There are no miracles, otherwise you could say it's a miracle that it works. If you hypothetically cut off all L3 memory, wouldn't the performance drop be an IPC drop? Will BTB make up for it too?
After all, Core will wait longer for data and will see a measurable drop in IPC. Remember, I'm not...
So why does AMD provide an IPC increase for games in Zen 3, when it is known that this applies to a larger number of cores, e.g. 8, and where it is known that the increase will result from a common and large L3 for all 8 cores without division into CCX? Can you explain this to me?
Isn't it the...
I know this graphic (since it was published online) with a percentage breakdown of how much is allocated to a given part of the core.
My question is still: doesn't the RAM controller, L3 cache capacity and design, etc. affect IPC?
If you reduce RAM bandwidth and increase access latency, won't...
Note that not all tests are 1T. AMD shows IPC growth curve 8 cores vs 8 cores.
Do you think that the L3 cache in Zen3 has absolutely nothing to do with the achieved IPC?
Zen 3 is a new and better design than Zen 2, adding approximately 15% more transistors to the core logic (excluding L2).
Additionally, the brand new L3 Cache design shared across 8 cores without splitting into 2 CCXs of 4 cores each had a significant impact on IPC.
Honestly, I don't believe in an average IPC increase of +10%. This is actually some point on the IPC growth curve for a specific task.
I think it will be closer to +20%.
But I guess I'm not very wrong if I guess that the IPC growth curve for Zen 5 will be from +1-5% to +40-50% ;)
AMD must consider the entire spectrum of workloads, not just games. Zen5 is designed not only for consumer computers, but also for Epyc.
Are there examples of profiling for other workloads/applications?
This is one of many factors and I am not saying it is the most important one.
This is the only way to find out and compare with Zen because LionCove separates the FPU ports from the ALU ports.
itsmydamnation
"Amd has far more dry powder in terms of architectural resource consumption and they are about to spend it , amd kept up with Intel while doing it with a sizablely smaller core."
My theory is that Zen benefits greatly from the schedule and execution ports, separate for the FPU...
Any tests? At what clock speed? No one is going to change what Zen 5 and LionCove are by saying positively or negatively about the uarch they choose.
Interestingly, however, seeing an increase in only two points of the architecture from 6 to 8 (+33%) Dispatch/Rename and from 4 to 6 (+50%) ALU...
Does a project from scratch have to mean such a large expansion that the project achieves an average of 40% higher IPC?
I think you are overestimating the phrase "new project from scratch".
A new greenfield project can also average 10-15% higher IPC.
Apple had no competitive pressure. It is...
I wanted to emphasize that in the past, even if there was a very large IPC jump, it was only against the background of the poor solution of the previous generation. Find another example if there was an exception.
You claim that Intel has been stagnant for 10 years, and yet AMD has not managed to significantly overtake uarch. Zen1 barely caught up with Broadwell (Haswell with minor tweaks). If it were that easy, they would have crushed Zen1 by now.
Since 2017, AMD and Intel have been going together like...
Athlon (K7) gave a big boost to IPC only because K6 was quite average compared to the competition (PII), and considering the FP load, very weak. The Athlon K7 with a much larger number of transistors - 22 million (without L2) barely overtook the Pentium III (9.5 million transistors without L2)...
I gave a general summary of decoding + sending from uop Cache because the LionCove diagram is of too low quality and does not specify how much it is for the decoder.
GoldenCove has 14 uops, including 6 from the decoder and 8 from the uop Cache.
LionCove has 24 uops, but it is not 100% sure...
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