That was M3 (at least that's what I saw reported, I never saw a link to an actual source for that claim)
Nevertheless, increasing L1 latency is not in any way equivalent to increasing pipe stages. There are plenty of reasons you might increase cache latency that have nothing to do with...
So if Apple is supporting SME now, do they still need their AVX instructions? Do those do anything that SME instructions can't? AFAIK SME requires ARMv9, so does that mean M4 is ARMv9?
Maybe it went like this - Apple was not ready to implement ARMv9 yet (and maybe that was dependent on the...
If they're increasing pipeline stages it would show up in instruction latencies. You're doing plenty of low level testing on Apple Silicon hardware, have you seen instruction latency increasing?
I'm skeptical. I think they're just taking advantage of what the process gives them. When TSMC shows...
I'm still not convinced of that. Intel may have originally planned to use N3 (before it was known to be flawed and became known as "N3B") a few years ago when "Intel buying TSMC N3" was on the news - and note that those rumors had Intel getting in AHEAD OF Apple on N3. Which would have happened...
If they want to kill off M3 as quickly as possible why did they just release the new MBA two months ago?
I think they always want a little distance between MBP and MBA, so the MBA will tend to be upgraded a bit later after the initial surge in sales from the new MBPs. So if they do new Macbook...
Given the way they've been ramping clocks the last few years, they'll exceed 5 GHz in two years. At some point I have to think this is going to be problematic for Apple's focus on low power. Curious to see how this does power-wise when running at max clock vs M3.
Apple often keeps two generations of a product around so they can have a lower price on the older model, but with M3 being supplanted by M4 so quickly they didn't get many M3 based products out the door.
But if they wanted to quickly drop M3 why did they introduce the M3 Macbook Air only two...
The reason why they did the compare to M2 instead of M3 is blindingly obvious to anyone who is paying attention. They were announcing iPad Pros, and the previous iPad Pro contained an M2! Why would they compare with the M3, when there never was an M3 iPad Pro?
When they do a new Mac Pro or Mac...
I remember everyone thought the same thing when they announced a 70% ST gain for A9, then it turned out to actually be 70% faster in real life.
A 50% MT gain is trivial, I did the math for it a few posts ago. They only need a single digit IPC gain on the P core, or a low double digit gain on...
There is unlikely to be that much interdie variation, certainly not at the level Apple is binning. Apple's speed binning is pretty lax since it is pure pass/fail, so the threshold must be set such that almost every functional die is a pass. They could get at least 10-20% more ST if they binned...
Yeah the node that made binning complex for Apple was N3B because it is so bad. N3E is back to normal TSMC yields, where Apple's "bin on defects in large structures" strategy to gain another few percent of usable dies makes sense.
It is interesting that they switched from binning on defective...
Based on the 'best' scores in GB6 ST Apple gained about 15% from M2 to M3. Apple E cores tend to be worth about 1/3 of a P core, so an 8 core M2 had 5.3 cores vs 10 core M4 having 6 cores, accounting for 12%. From N3E TSMC says you should get 6-7%. If you multiply all that together (can't add...
Regarding the Gurman article on using M4, I wonder if his source was the iPadOS 14.5 betas containing indications of iPad 16,x and the T8132. That information was apparently around for a while before Gurman's article, so maybe he doesn't have any actual sources for this beyond that. Others might...
I still don't buy it. I saw other reports that Apple was building custom chips for their AI servers. That I could believe. It makes zero sense to install a bunch of Apple Silicon chips just to use the tiny corner that's labeled 'NPU', or the slightly larger piece that's labeled 'GPU', and waste...
I think that's an outmoded way of looking at things. Back when chip architects were designing a "CPU", having two or three teams leapfrogging each other and when one finishes the 2024 design starting on 2026 or 2027 made sense. That's no longer true today when a chip design includes two...
Pre AI boom Samsung's processes weren't in the complete disarray they've been mired in for the last few years. Pre EUV TSMC seemed to have a small advantage, but that may have been less important to Nvidia than other stuff like capacity or price. Going with Samsung today would appear to be...
Of course they do. They are using "regular NA" EUV for Intel 4, 3, 20A and 18A.
At some point ASML will be able to meet demand for EUV and the order backlog will begin to shrink. Not sure if they have reached that already, but I did read recently that ASML's overall order backlog is half what...
Yeah I read that story shortly after it came out, but it is rather worrying that Intel seems to be betting the company on being able to take DSA to mass production. I sure hope they have a backup plan if it ends up having too high a defect rate or whatever when they go from running a few wafers...
Apple also isn't shy about having new products for which they can't fully satisfy demand, or at least they weren't in the past. They've got better as the production scale as increased over the years, but the shelves in Apple stores used to be empty after a new iPhone launch. If you didn't get...
High NA scanners cost more than twice as much (and are much larger and use more power and are in very short supply and are brand new and more likely to have teething issues) so using them for process steps where they provide no benefit over regular EUV scanners makes no sense. I mean, you could...
Six months from start of mass production to first shipments isn't set in stone. It is probably three months at the outside from start of mass production for first wafers exiting the line. You need to do testing, packaging, etc. and then of course assemble the products they go into but if the...
Which is what I've been saying for months, ever since the die photos showed no I/O pads. There were still a lot of people saying there's no way the M4 would come out in October only a year after the M3. Well I guess I got that part wrong too, but less wrong than the people pushing '18 months'...
Nah I was skeptical but now I'm not, that is EXACTLY the kind of evidence I was looking for to believe that the new iPads will have M4. If they have M4 in iPad Pro now I don't think we will be waiting until the next iPhone launch to see M4 Macs either.
Sure, but Apple's management has been pretty good about not having a short term outlook focused on quarterly stock prices. They aren't going to go to a bunch of effort to push out M4 early because they want to goose the stock price in May rather than October.
That's all cloud based, and all depending on Nvidia hardware. Apple's on device AI will be a totally separate category. If they were gaining a year I might agree with you, but four months is nothing. They wouldn't make major roadmap changes to gain fourth months in a market that doesn't yet exist.
Its irrelevant to Apple's fortunes whether they release something with "AI" in May or October, there is no need to "catch up". Especially when AMD and Intel have nothing at all on that front yet. Who is their supposed competition, Nvidia? They play in datacenter AI which is a whole different...
Well one thing that would be in favor of this is if Apple plans to show off their new cores in Apple Silicon first, and iPhone gets them later in the year - the opposite of how things have been done up until this point.
Because TSMC's node timing seems to be totally off from what they have been...
You can tell from that table alone that Apple is not going to be concerned about minor variations in price. They went from 119 to 142 mm^2 between M1 and M2, despite N5P being a bit denser. That clearly increased their cost, but M2 would still be less than $50 per chip (not including the fancy...
Well there's a reason that someone with an agenda is posting scores showing the Mac laptop being "demolished" and then makes a lame excuse for why he won't post the battery scores that provides ample reason for the performance discrepancy.
If you turned that Blender benchmark into "how much...
I don't buy it. I suppose theoretically there would be enough time for TSMC to have run them enough N3E wafers for a lower volume product like the iPad Pro, and if they had the core design for the M4/A18 done a few months earlier than usual it would be possible.
But "theoretically possible"...
Given the rather large overlap between what GPUs need to do and what NPUs need to do, I suspect they will be combined. That's already effectively true for Nvidia's high end discrete stuff, but I would expect say Apple will combine them before long. They haven't had reason to up until now because...
If it benefits Apple's main customers - the ones who run iOS/iPadOS/macOS on their hardware - by allowing Apple to make non-compatible changes to the AMX instructions but disadvantages the tiny minority running Linux I think even the ones running Linux would concede that's what Apple should do...
Apple doesn't care about Linux on ARM Mac. They haven't impeded the efforts of the Asahi Linux crew but they sure aren't making extra work for themselves by directly supporting them either. So no, they won't make those libraries available for Linux.
Do you think the (at the very most) one...
In the last update TSMC was pretty clear that N2 did not have BSPDN, but it would be made available as an option six months later. That N2+BSPDN was not N2P, it was just N2 with BSPDN.
So this talk about N2P losing BSPDN is confusing. Is there no BSPDN until A16, or is that the first node that...
Apple doesn't refuse to admit they exist, they want people to use library calls to use them. That way they can change the way the instructions work without breaking old software. Nothing stops someone from using AMX instructions, but if their code breaks with M4 they can't complain because Apple...
Why would you expect more SLC is going to lead to higher ST performance? Especially in something like Cinebench?
I'll bet the working set size of the executable (i.e. the inner loops where the work is done) is easy fits in 16 MB, in fact likely fits in L2i. The data it works on will be larger...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.