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Says who? Just because Intel cannot do it, does not mean it is not possible for anyone else.

Hope everything will turn right for you. First half of last year was awful for me, but all ended well. Best of luck!

Depends what you call process leadership. Intel of yore had both superior process and huge volume. I will gladly say that Intel has leadership when they can match TSMC volume. Until then it's basically a power point victory. Now, you have to start from somewhere...

Now that is some real microarch pron:p Me want more!:yum:

MI300 and next gen MIXXX just won two high profile contracts for supercomputers in Germany, Hunter and Herder. Latter one is exascale.

I hate to be that guy, but it has to be said. What do Meteor Lake and Phoenix have with Zen5? We have appropriate threads for those topics. Sorry for being tightass.

If these diagrams are true, then there is new IO die also for Turin since there is support for cxl2.0 and 6000MT DDR5. CCD in standard Turin are losing some bandwidth. Turin dense CCD are using some dual ring setup so L3 latency is going up but for cloud it should not matter much. Edge platform...

Bihevioral analysis, urban development models, logistics optimisation, chip design, marketing, materials research, production processes optimisation, etc.....

Yes it does. Go on chips and cheese site, they say that there is quite bit more trips to RAM, and that workloads can go over 8MB of cache per thread.

So we return bac to my OGP about topic. It is cost and revenue opportunity. Everything is finite resource, hence use that limited resource as efficiently as you can - produce MI300 and MI400 as much and as fast as you can. There is AI craze going on out there.

So what is it? According to your statements, latency sensitive part of code is problem, not hardware. But to solve those issues in tiled architectures, to be precise multi chiplet architectures you need to use advanced packaging. Which again, is not used according to your statements. Well, no...

Here is my take on RDNA4 and lack of MCM high end SKUs, for what is worth. I think AMD scrapped those not for having trouble with software side but money. Or to be more precise revenue opportunity. There is finite amount of packaging capacity and due to AI craze they choose to spend it on MI300...

I have to say I'm quite surprised with this earnings report. Enterprise and embedded (xilinx), as well as gaming (consoles) were underperforming in my opinion. Biggest suprise is xilinx, to be honest. Client was doing well, as I expected. AMD could have better supplied market and achieved better...

Today is AMD's Q323 financial report. Although AMD does quite conservative forward looking statements, they are usually spot on (they do around 7-8% better). I am of opinion that client will be substantially better than last quarter, gaming also due to consoles (I think N32 still doesn't have...

That is billion dollar question, literally😉

Thank you @Hitman928! I didn't know about preanno Thanks you! I didn't know about preannouncement. My guess was right. Client segment was down, with caveat that they had better operating income.They managed to clear stock of old products. Enterprise is abysmal, half billion down in...

Today is Intel's Q3 financial report. Opinion guys? I think their client numbers will not be as good last quarter despite Q3 being usually the best in industry in general. Enterprise will be another abysmal quarter for them, in my opinion.

I can give you anecdotal evidence, for what is worth. I have played for years paradox grand strategies like HOI. It's never GPU bottleneck, believe me. Game likes CPU. And game keeps lots of data in flight so more cache the better. Game sessions can last for months, so that is lots of in flight...

Power too

Context is PPC or IPC, whatever you want to call it and AMD's ability (disability) to match those of apple cores, even if Zen5 is high clocking core.

Some posts remind me of Zen1 prelaunch discussions, when AMD could not match broadwell/skylake because reasons. Now also AMD cannot match Apple because reasons.

With a caveat that we don't know L2 and L3 capabilities.But I am just repeating the obvious. Your post is quite unambiguous about it. Two thumbs up

Edit and off topic: Boy what will Zen6 with new package do in this regard :)

What about vcache chips? I have feeling that we will see more gains than with previous Zen gens. These wide cores demand more bandwidth.

Since you are talking about steady FP benchmarks, latter clock distribution makes more sense. Unless, Z5 and Z5c have different FP capabilities like 512b and 256b width. Then it is better to have more power on full cores.

I would still not be worried. 4 cores can suck lots of juice at high clocks. They can use more than half of allowed PPW @88 W.

Cores can be clocked independently. So they need to make good driver that OS knows where to put priority tasks.Amd already has good onchip PWM. I don't think they will push dense cores above efficiency point.

@androc_thurston When you said that Venice will be silly expensive did you mean that because of fabbing cost or packaging cost. Packaging should not be that expensive in 2,3 years, unless production capacity will still be strained? Sorry guys for off topic.

What about x(3d) factor? That is big unknown. And thank you!

Huh.... Well, 25 % more power for 33% more cores and 25-ish % ( on average) more "IPC" is good tradeoff in my book. Guess we will have to wait for Zen6 for substantial ppw improvement with compete SoC/package overhaul.

You can increase socket power, but that does not say anything about ppw. You have inside knowledge, but I will be floored if efficiency does not go substantially up.

I am of opinion that they will hit 1.2-1.25 on average.Clocks will stay sameish. What will change most is ppw. I think it will shoot through the roof ( at sane clock speeds ~ 4ghz).

These leaks about layout and number of ALUs and all are nice but we will not know almost until launch what are those resources capable of.Like instruction exec latency. Zen 2 to Zen 4 have not seen ALU count change but they got vastly improved. We know for instance that L1 changed from this...

I am personally not that much interested in part of widening core execution resources, it is important, but how to feed core(s) and SOC. As @itsmydamnation always says, executing data is easy, moving data is hard. Will AMD ditch on CCD L3 to expand number of cores? How many cores per CCD, 8,12...

Nah, this would be like six wrongs does make a right :D

I have to say that I am impressed with Zen4. I am looking forward for Phoenix and Dragon disclosure at CES. Those chips will be something else,my 5900HX will look like is from dark ages.

http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=threads/speculation-zen-4-epyc-4-genoa-ryzen-7000-etc.2571425/post-40737983 Ha! Guess I was right! :p For all THE WRONG reasons! :D If you have ever been in a situation where you had to resolve complicated math function and you screw up starting parameters and...

Look, nVidia has just posted preliminary financial report. Revenue down 1.5 billion than expected with 1.5 billion of obligations(read inventory and payed production). All that means that those card are not worth the money they are asking. Don't buy, you're be wasting your money. That 3090ti is...

What if, and that is big if, stacked cache is for dual GCD models? So, you use up half of your connects to memory(MCDs) to connect your GCDs(two to be exact). Now you are bandwidth starved. Stack additional cache on MCDs. Voila!

https://videocardz.com/newz/nvidia-reportedly-wants-to-cut-tsmc-orders-for-next-gen-rtx-40-gpus-5nm-wafers-amid-lower-demand Well this is kind of interesting rumour. It makes sense for Apple and Nvidia, but AMD? They have such wide portfolio of products made on 6/7 nm and they are still in...