AMD “Next Horizon Event" Thread

[csbin]

7nm Zen2，EPYC 2，7nm Vega20，Navi，one more thing？

 

[cortexa99]

What I heard about Zen2:

1. IPC higher than expected
2. memory latency is mainly improvement
3. AVX performance improve(still no AVX-512)
4. 7nm frequency preview
5. much precise turbo boost

 

[Panino Manino]

There's a lot of big dreams about Rome, but really, it Zen 2 comes just meeting AMD expectations, isn't enough?
+10% IPC, -10ns latency, +300-400MHz base and top frequency, "improved" FPU.
Just this isn't enough?
10 months after comes the new refresh with +100MHz and -5ns latency.
Better drivers, better BIOS, enough to stay competitive, right?

 

[LTC8K6]

I want AMD to do better than that because I think Intel needs a big kick in the butt right about now.

 

[Hitman928]

Anyone know what time the event starts?

 

[LTC8K6]

Noon on the east coast.

 

[coercitiv]

Anyone know what time the event starts?

https://www.anandtech.com/show/13547/amd-next-horizon-live-blog-starts-9am-pt-5pm-utc

 

[Panino Manino]

https://twitter.com/IanCutress/status/1059835252959408129
https://twitter.com/IanCutress/status/1059833040057188352

Ian toying with my expectations.

 

[thecoolnessrune]

It's cheap, but part of me hopes that AMD comments about the "cheap glue" Intel is using to bond Cascade-Lake AP together.

 

[lixlax]

Is there going to be any stream/blog or is this a closed event?

Edit: stupid of me, there is even at Anandtech.

 

[Despoiler]

Valid livestream https://www.youtube.com/watch?v=GwX13bo0RDQ

 

[Lodix]

https://youtu.be/GwX13bo0RDQ

 

[coercitiv]

Modular System Design

 

[HurleyBird]

Doubled FP and Load/Store

 

[Tuna-Fish]

256bit AVX and doubled load/store width.

 

[Topweasel]

Awsome. AVX-2 Native support.

 

[The Stilt]

A wide(r) core, finally

 

[Hitman928]

Chiplet design confirmed.

IO chip is 14 nm.

 

[Tuna-Fish]

Chiplets are real.

 

[Panino Manino]

HOLY SMOKES!

 

[Topweasel]

Chiplet confirmed, confirmed.

 

[beginner99]

Chiplets and 14nm IO die are real. That is the big take-away for Zen 2.

256-bit floating point, higher IPC. Else not much info on clocks or actual performance.

 

[Tuna-Fish]

The next big question I have is how much cache does that IO die have? To host all that IO, it needs a large circumference. So a lot would fit, even at 14nm.

 

[lixlax]

13,2b transistors @ 331mm2 for vega 7nm.

 

[beginner99]

1 TB/s memory bandwidth for Mi60.

pcie 4.0!