NP, we should know more in the future. I have no doubt though
So, you still think LPDDR6 will become popular in 2027 even there are reports of coming in end of 2025?
Last edited:
NP, we should know more in the future. I have no doubt thoughDubious leaks.
So, you still think LPDDR6 will become popular in 2027 even there are reports of coming in end of 2025?
What I am saying is:
Yes, LPDDR6 will come in late 2025, with, support from Snapdragon 8 Gen 5 and Dimensity 9500. It will see wide adoption in flagship Android phones of 2026.
However, it will not be the full fat speedy LPDDR6-12800. I believe for initially (late 2025, entire 2026), it will be limited to a lesser speed such as LPDDR5-11000.
Full speed LPDDR6-12800 won't be coming until 2027. That's what I think.
| Date | Phone SoC | CPU cores | Memory Interface | Date | Mobile SoC | Node | Memory Interface | |
|---|---|---|---|---|---|---|---|---|
| Q4 2024 | 8 Gen 4 | Phoenix 2+6 | 64-bit LPDDR5T-9600 | 2025 | X G1 ? | N3E | 64-bit LPDDR5T-9600 | |
| Q4 2025 | 8 Gen 5 | Pegasus 2+6 | 64-bit LPDDR6-12800 | 2026 ? | X G2 ? | N3E | 64-bit LPDDR6-12800 | |
| Pegasus 12P +++ | 2026 ? | X Elite G2 ? | N3P ? | 128-bit LPDDR6-12800 | ||||
| Q4 2024 | D 9400 | X5+X4 4+4 | 64-bit LPDDR5T-9600 | 2025 | ? | N3E | 64-bit LPDDR5T-9600 | |
| Q4 2025 | D 9500 | X6+X5 4+4 ? | 64-bit LPDDR6-12800 | 2026 ? | ? | N3P | 64-bit LPDDR6-12800 |
This is a fundamental misunderstanding of how modern DDR works or is developed. CL and other primary timings within the same bank, like tRCD, tRP, or tRAS's impacts on performance can be minimized with enough parallelism at the Bank, Bank Group, and Rank level [Figure 1]. You'll find that in this research paper characterizing how different DRAM architectures perform, that in workloads where latency is paramount, DDR4 outperformed DDR3 even with a higher CL latency in ns [Figure 2]. Much of what determines latency in modern DRAM is no longer timing delays alone, but how concurrently you can service requests from the CPU [Figure 3]. Those queuing delays are caused by resource conflicts at the bank and bank group level, where accesses must be serialized within a Bank/BG, which takes longer than going to a different bank or bank group. This also doesn't address the other ways that DDR5 hides latency through a wider prefetch, split 32-bit subchannels, and higher bandwidth, which itself lowers latency since the closer you approach your DRAM's theoretical limits, the higher the latency gets as you work your DRAM's resources more and more [Figure 4]. https://user.eng.umd.edu/~blj/papers/memsys2018-dramsim.pdfDDR5 not going beyond 8800 MT/s is disappointing.
DDR6, whenever it gets released, is going to have terrible CAS latency compared to DDR5 and the same old crap will ensue where you have to wait a year or two for the newer RAM standard to get fast enough to leave the older standard behind. This, in my opinion, is the great RAM speed scam.
Why do they even release a new generation of memory when the previous more mature standard already beats it at its fastest available speeds? DDR5-4800 vs. DDR4-4000 was a sick joke.
Why don't these "brilliant" engineers actually try to bring the latencies down to an acceptable level before proudly touting their new technologies? It's actually not their fault. They would never release something half baked into the world if it were up to them. It's the profit craving executives/bean counters calling the shots at these big companies. The bane of every techie's existence.
/rant
real and feral my man.This is a fundamental misunderstanding of how modern DDR works or is developed. CL and other primary timings within the same bank, like tRCD, tRP, or tRAS's impacts on performance can be minimized with enough parallelism at the Bank, Bank Group, and Rank level [Figure 1]. You'll find that in this research paper characterizing how different DRAM architectures perform, that in workloads where latency is paramount, DDR4 outperformed DDR3 even with a higher CL latency in ns [Figure 2]. Much of what determines latency in modern DRAM is no longer timing delays alone, but how concurrently you can service requests from the CPU [Figure 3]. Those queuing delays are caused by resource conflicts at the bank and bank group level, where accesses must be serialized within a Bank/BG, which takes longer than going to a different bank or bank group. This also doesn't address the other ways that DDR5 hides latency through a wider prefetch, split 32-bit subchannels, and higher bandwidth, which itself lowers latency since the closer you approach your DRAM's theoretical limits, the higher the latency gets as you work your DRAM's resources more and more [Figure 4]. https://user.eng.umd.edu/~blj/papers/memsys2018-dramsim.pdf View attachment 94960
View attachment 94964
View attachment 94965
View attachment 94966
This is true, if there is sufficient parallelism in your workload that you can make use of those concurrent results. This is true of, for example, terminally OO java/C# business software that is generally both very thread-parallel and latency-bound.You'll find that in this research paper characterizing how different DRAM architectures perform, that in workloads where latency is paramount, DDR4 outperformed DDR3 even with a higher CL latency in ns [Figure 2]. Much of what determines latency in modern DRAM is no longer timing delays alone, but how concurrently you can service requests from the CPU
Currently DRAM has entered a significant scaling conundrum which can only be surmounted by a pretty significant change in structure to a capacitorless device design.Because DRAM cells haven't improved in like 30 years
That's only about 1.33x faster than the LPDDR5T speeds announced by SK Hynix January 2023 and shipped the following November.hopefully we should see LPDDR6-12800 soon...it is going to be game changer
I was under the impression it had more to do with data routing and associated physical pin arrangement.However with 50% extra memory bandwidth, OEMs have to put in much more transistors to feed the bandwidth. That's why the die area will get bigger even with more advanced process. That's why AMD is splitting the x86 SoC into two chiplets
That's only about 1.33x faster than the LPDDR5T speeds announced by SK Hynix January 2023 and shipped the following November.
12800 is certainly an improvement, but hardly a "game changer" unless it is achieving that bandwidth at significantly better perf/watt than LPDDR5T.
I was under the impression it had more to do with data routing and associated physical pin arrangement.
ie you literally can't just keep shrinking the memory I/O because of the physical pin constraints.
Clearly you have underestimate the impact of LPDDR6. I am mostly referring to PC market, with 64-bit memory bus LPDDR6, OEMs could design smaller SoC with the memory bandwidth of past 128-bit LPDDR5X. By removing half of memory pin connector, OEMs like NV could design SoC with Xbox series S's graphics performance with better battery life..
Clearly you are OVERESTIMATING the impact of LPDDR6, given that you started a whole thread with crazy hyperbole like "the mother of all CPU upgrades" and believe everyone is going to be rushing to implement it as soon as possible cost be damned! Never heard of diminishing returns, I guess?
Did you say the same thing about LPDDR5, given that it was a similar (if not larger since there was no LPDDR4T) bump but coming from a lower bound? If you didn't hype LPDDR5 this much, why do you think LPDDR6 will be more impactful than LPDDR5 was?
And you linked a study that simulates a comparison of DDR3 to DDR4 at nearly identical timings, but with the DDR4 sporting higher transfer rates...This is a fundamental misunderstanding of how modern DDR works or is developed.
1. A lot of thread parallelism isn't necessarily required for sufficient DRAM parallelism, though it much helps.This is true, if there is sufficient parallelism in your workload that you can make use of those concurrent results. This is true of, for example, terminally OO java/C# business software that is generally both very thread-parallel and latency-bound.
It is not true of a lot of latency-bound software that doesn't have a lot of TLP, notably, games. For a lot of software, the measure that matters most is just how quickly will the memory return a response to a single request into a closed row, and for that early implementations of new memory standards are generally somewhat worse than the late high-end memory of the last standard.
Firstly, I don't know how this bit on DDR4 vs DDR3 disproves my point. Secondly, I know for a fact that you're basing those latency numbers from Aida, a benchmark that pulls paltry bandwidth and measures idle, not loaded, sequential access times from DRAM, which is nothing like games that are inherently speculative and random access. In this DDR4 vs DDR5 study, yes, DDR5 at iso bandwidth to DDR4 has slightly higher sequential access times, but has lower random latency, something games take advantage of. I'm not saying DRAM latency hasn't taken a step back in a few ways, it has, but the bandwidth improvements have far outweighed the minor increase to sequential latencies. https://drive.google.com/file/d/1LelSBpNknT9wgqX3z2j6OUh2Md_3Vx06/viewAnd you linked a study that simulates a comparison of DDR3 to DDR4 at nearly identical timings, but with the DDR4 sporting higher transfer rates...
Bit different of a case compared to what consumers saw with DDR5-4800 vs. DDR4-4000. DDR3 could get into 40ns range easily, DDR4 eventually got into 30ns ranges especially at 4000mhz, DDR5 is still at 50ns range at best and usually 60ns on average. In other terms DDR4 is actually about two generations behind on what was the average latency trend. Even DDR5-8000 doesn't crack the 50ns barrier despite its crazy bandwidth.
Latency in DRAM has objectively taken a step back, though it's true even 60ns (and even higher) is absolutely acceptable for 99% of tasks out there. With the latest generation between DDR4 and DDR5, there is objectively a gap in progression with relation to latency vs. bandwidth.
In November 2023, Valve Product Designer Lawrence Yang told Bloomberg that the Steam Deck 2 will feature a "next generation" power upgrade but won't be available for two or three years. Yang also told Axios, "In the next two or three years, we're confident that something will be what we would consider appropriate for a proper Steam Deck 2 device."
All premium FF AMD SoCs are 128b.The only way to get power upgrade within same TDP is upgrade to newer process AND using 64-bit LPDDR6. By reducing half of memory pin connector thus power savings, Valve and AMD are able to double the FP32 within same power target. Based on timings, we should be expecting Steam Deck 2 in early 2026.
Too early for u, sorry...All premium FF AMD SoCs are 128b.
Don't.
It's some serious engineering sheee-it. I tried to understand it but then decided that my brain is too fragile to expend on stuff I have no use for.My initial thought was data query.