Info LPDDR6 @ Q3-2024: Mother of All CPU Upgrades

[soresu]

@FlameTail This seems to be what the tweet is referring to.

It seems to have something to do with the data pins on DDR (DQ), and there are also some sort of control or clock pin (DQS) called a strobe that exists for every certain number of DQ pins.

 

[Hitman928]

@FlameTail This seems to be what the tweet is referring to.

It seems to have something to do with the data pins on DDR (DQ), and there are also some sort of control or clock pin (DQS) called a strobe that exists for every certain number of DQ pins.

Yes, it is the data bit. I believe it comes from the convention for D flip flops where the D is the input and the Q is the output. Since RAM can be written or read, they call it DQ. Going off of memory since I don’t do digital design though, so someone can correct me if that’s not correct.

 

[soresu]

Yes, it is the data bit. I believe it comes from the convention for D flip flops where the D is the input and the Q is the output. Since RAM can be written or read, they call it DQ. Going off of memory since I don’t do digital design though, so someone can correct me if that’s not correct.

Ah yes they referred to it as bidirectional so that makes sense.

The letter terminology less so, makes me think there is latin or greek involved 🤔

 

[igor_kavinski]

Some clues here: https://www.intel.com/content/www/u...tushelp/17.0/reference/glossary/def_dq_io.htm

 

[soresu]

Some clues here: https://www.intel.com/content/www/u...tushelp/17.0/reference/glossary/def_dq_io.htm

Great minds!

I posted that for Flametail above 😎

 

[Tigerick]

Steam Deck 2 Speculation



Above picture shown the changes of PCB of Steam Deck OLED compared to OG Steam Deck. The memory chips have been reduced to 2 pcs. Memory bus still remains the same, i.e.. 128-bit. Each memory chip is connected via 64-bit memory bus which provided 102GB/s memory bandwidth. With upcoming 64-bit LPDDR6 which provides same bandwidth, Steam Deck 2 could further reduce memory chip to one piece only. SoC also will benefit by removing half of memory connector. Therefore, combining with advanced process like N4P, Steam Deck 2 could double FP32 numbers while maintaining same battery life.



In games like Cyberpunk 2077, SD2 should provide much better fps (~30-50% ?) in 800p resolution while still providing excellent battery life:



This is what Valve wanted in next generation power upgrade SoC empowered by 64-bit LPDDR6.

NV has been rumored to release handheld console. It seems like NV is going to use same ARM SoC in upcoming Surface X. The SoC going to connect with 64-bit LPDDR6 which provides about 4 TF in FP32. This is the same TF as Xbox Series S, can't wait for Jensen to announce Pocket XSS in the future...

 

[igor_kavinski]

TBH, waiting for LPDDR6 to increase performance and battery life especially with AMD SoCs sounds absurd when AMD has the solution right under their noses: V-Cache or Infinity Cache!

 

[soresu]

Steam Deck 2 Speculation

View attachment 95445

Above picture shown the changes of PCB of Steam Deck OLED compared to OG Steam Deck. The memory chips have been reduced to 2 pcs. Memory bus still remains the same, i.e.. 128-bit. Each memory chip is connected via 64-bit memory bus which provided 102GB/s memory bandwidth. With upcoming 64-bit LPDDR6 which provides same bandwidth, Steam Deck 2 could further reduce memory chip to one piece only. SoC also will benefit by removing half of memory connector. Therefore, combining with advanced process like N4P, Steam Deck 2 could double FP32 numbers while maintaining same battery life.

View attachment 95446

In games like Cyberpunk 2077, SD2 should provide much better fps (~30-50% ?) in 800p resolution while still providing excellent battery life:

View attachment 95449

This is what Valve wanted in next generation power upgrade SoC empowered by 64-bit LPDDR6.

NV has been rumored to release handheld console. It seems like NV is going to use same ARM SoC in upcoming Surface X. The SoC going to connect with 64-bit LPDDR6 which provides about 4 TF in FP32. This is the same TF as Xbox Series S, can't wait for Jensen to announce Pocket XSS in the future...

I doubt that Valve will go for double spec.

Remember that the Van Gogh SoC is only 2/3 the CU count of Rembrandt, which they almost certainly would have been told was in development.

To me that says they went for 8 CU for cost and/or power reasons.

So while them just jumping straight on Strix Point 16 CU or something like is possible, I wouldn't bet on it.

 

[Tigerick]

AMD's Speculation on LPDDR6 solution

Due to ever increasing memory bandwidth of LPDDR6, (Strix Point's die size is around 225mm2) AMD could switch to ARM platform in the future. It is game changer for AMD from technical AND business points of view. TLDR, please follow up in the following thread:

AMD's Future APU Gone ARM

AMD will likely be providing monolithics ARM SoC with 64-bit and 128-bit LPDDR6 support. Meanwhile, AMD will keep upgrading Sarlak's family as shown below:-



Last time, adroc said Sarlak's performance is about 7600M level. Based on memory bandwidth, yeah it is comparable. The only thing is RX7600M is build by N6 process with 28 CU @ 2.41GHz. Meanwhile, Sarlak's iGPU is having 40CU build by N3E process. Why do AMD need so many CU for RX7600M's performance?

My theory is AMD is planning to support LPDDR6 support on the same silicon. AMD could potentially bump the memory controller from 4.3 Gbps to 6.4 Gbps, then total memory bandwidth will increase to 410 GB/s.

If AMD is releasing Sarlak with LPDDR5x first, Sarlak6 will come one year later with 50% memory bandwidth improvement. In IT world, anything above 50% improvement within same interface is considered big upgrade.

However, if AMD straight away launch Sarlak with LPDDR6 support due to early availability, then we should be expecting three times bandwidth improvement.

Let's see how the thing turn out....

 

[Tigerick]

Yeah this is something that I have been wondering about this thread as well.

Compute power increases with time, and it natural that memory bandwidth increases too (if anything, memory bandwidth is not as increasing as fast the compute is). So it's natural to have new memory standards come up with time. Now we have LPDDR5X, then will come LPDDR6, then LPDDR6X, then LPDDR7... the cycle continues.

If you spend a little time read the table I provided in the frontpage, you won't say above words. I know you don't know how to calculate, let me list down the % for you:

	64-BIT	+ %	+ GB/s		128-BIT	+ %		256-BIT
LPDDR4X-4266	34 GB/s
LPDDR5-6400	51 GB/s	+ 50%	+ 17 GB/s
LPDDR5X-8533	68 GB/s	+ 33%	+ 17 GB/s		136 GB/s			273 GB/s
LPDDR6-12800	102 GB/s	+ 50%	+ 34 GB/s		205 GB/s	+ 50%
LPDDR6-14400	115 GB/s	+ 13%	+ 13 GB/s		230 GB/s	+ 13%
LPDDR6X-16000	128 GB/s	+ 11%	+ 13 GB/S		256 GB/s	+11%

Do you see the difference between each memory speed? LPDDR6-12800 provides biggest jump in memory bandwidth within same interface. Even the successor of LPDDR6, LPDDR6-14400 and LPDDR6X-16000 are only providing 11-13% improvement in memory bandwidth. Clearly with 50% bump in memory bandwidth, there is going to have big changes coming. And that's the reason I created a thread to discuss everything related to LPDDR6. Mind you, we may not see LPDDR7 in the future cause LPDDR6X might hit production bottleneck.



Another game changer related to LPDDR6 is Mediatek and Qualcomm's mobile phone flagship SoC will be used as notebook SoC. Due to same 64-bit LPDDR6, Mediatek and Qualcomm will likely use the same die for flagship and mobile SoC as listed above.

In fact, as reported earlier, Qualcomm might be supporting LPDDR6 in upcoming 8 Gen4; even though 8 Gen 4 supposedly be using LPDDR5T. Clearly, the memory controller on the SoC could support both memories.

In the future, we could see army of ARM SoC from Qualcomm, Mediatek, AMD and NV fighting for PC market share. It might not be directly related to LPDDR6 but Mediatek and Qualcomm are going to use it in order to spread the high BOM cost.

PS: Next time if you are not interested or not familiar on certain thread/topic, you could just stay away. Instead, you are wondering what is the purpose????

 

[Tigerick]

Apple's Unique LPDDR6 Solution


Shown above is the die shot of M3 SoC from Apple. Similar to SD, M3 is connected to 128-bit LPDDR5-6400 with 102GB/s bandwidth. What could Apple do to support upcoming LPDDR6? If Apple going to support 128-bit LPDDR6, the memory bandwidth will be doubled. Nah, Apple won't be so generous especially M-series is used on tablet as well. Then, it hits me that Apple's weird decision to reduce memory bus of M3 Pro from 256-bit to 192-bit bus....

Yeah, Apple going to implement something weird yet make sense if you understand the logic behind. For upcoming M4 series, Apple going to introduce 96-bit memory bus of LPDDR6 per channel as shown below:-



First of all, you have to understand Samsung, the biggest memory maker is making 24Gb (3GB) die as standard LPDDR6 die. Therefore, all the LPDDR6 memory chip will contain multiple layers of memory die, the most common one is x4 equal to 12GB. And that's the base memory size which connected to 64-bit memory bus. With 96-bit, Apple have to custom the pin connector on the memory chip to support extra 32-bit memory bus. The advantage is M4 will provide extra 50% memory bandwidth within single memory chip. Even with upcoming 64-bit LPDDR6X-16000 could only provide 128 GB/s bandwidth. Clearly, with 96-bit LPDDR6-12800, it provides Apple plenty of headroom for future generation.

And yes, Apple will keep using LPDDR6-12800 for many generations even after LPDDR6X arrive. Initially, Apple have to pay slightly more to Samsung due to custom design. With each faster LPDDR6 arrive, the current one will keep dropping price. And Apple will reap the benefits. Meanwhile, other OEMs will have to keep paying higher price each newer generation. Apple just keep selling newer generation of M-series with 12GB as standard. And that is game changer for Apple cause Apple no longer have to worry about ever increasing memory prices.

 

[Tigerick]

Another benefit of 384-bit memory bus compared to 512-bit memory bus is reduction of SLC cache as shown below:-


SLC cache is actually associated with memory controller. With 384-bit memory bus, the amount of SLC should drop from 64MB to 48MB.

 

[Tigerick]

Clearly you are OVERESTIMATING the impact of LPDDR6, given that you started a whole thread with crazy hyperbole like "the mother of all CPU upgrades" and believe everyone is going to be rushing to implement it as soon as possible cost be damned! Never heard of diminishing returns, I guess?

Most tasks are not limited by memory bandwidth with LPDDR5/5X/5T, meaning they would not benefit at all. Sure for stuff that is running up against that limit it will be a nice bump, but hardly the game changer you are hyping it to be.

Did you say the same thing about LPDDR5, given that it was a similar (if not larger since there was no LPDDR4T) bump but coming from a lower bound? If you didn't hype LPDDR5 this much, why do you think LPDDR6 will be more impactful than LPDDR5 was?

Clearly you don't know what you are talking related to LPDDR6. Are you even familiar with PC market to begin with?

Beside 50% improvement of memory bandwidth, I have listed down potential game changer related to LPDDR6 including Apple. Beside bandwidth related, game changer could mean big change in platform choice like AMD.

With Sarlak supporting 256-bit LPDDR6, AMD could finally has GPU performance similar to upcoming RDNA4. And do you even know about Sarlak or RDNA4?

Since you are familiar with Apple, 12GB LPDDR6 as standard could view as game changer cause Apple finally upgrade the RAM from 8GB to 12GB. As for future LPDDR6 memory configuration, Apple new memory interfaces will last for many generations.

If you think this is NOT game changer, please tell me what is your NOT game changer's configuration? I would love to hear about it.

 

[FlameTail]

Do you see the difference between each memory speed? LPDDR6-12800 provides biggest jump in memory bandwidth within same interface. Even the successor of LPDDR6, LPDDR6-14400 and LPDDR6X-16000 are only providing 11-13% improvement in memory bandwidth. Clearly with 50% bump in memory bandwidth, there is going to have big changes coming. And that's the reason I created a thread to discuss everything related to LPDDR6. Mind you, we may not see LPDDR7 in the future cause LPDDR6X might hit production bottleneck

Ha!

Counterpoint: LPDDR4X -> LPDDR5 was also a 50% jump. 4266 Mbps -> 6400 Mbps

So what's special about LPDDR5X (8533) -> LPDDR6 (12800)?

If anything it is expected. History doesn't repeat itself, but it often rhymes

Another game changer related to LPDDR6 is Mediatek and Qualcomm's mobile phone flagship SoC will be used as notebook SoC. Due to same 64-bit LPDDR6, Mediatek and Qualcomm will likely use the same die for flagship and mobile SoC as listed above.

Of course that's always an open possibilty. But I am skeptical about it, especially with regards to Qualcomm doing so.

You see, these flagship 64-bit SoCs come integrated with cutting edge 5G modems. They take up about 15-20 mm² of die area.

Not all brands want to put 5G in their laptops. So the added cost of the 5g modem but it's redundancy when not used, is a waste of money. Hence why all Snapdragon 8cx chips and now the Snapdragon X Elite don't have integrated modems.

 

[Tigerick]

Ha!

Counterpoint: LPDDR4X -> LPDDR5 was also a 50% jump. 4266 Mbps -> 6400 Mbps

So what's special about LPDDR5X (8533) -> LPDDR6 (12800)?

If anything it is expected. History doesn't repeat itself, but it often rhymes

You really don't know the way we compare beside %. I have updated the table to include how many GB/s has been increased from LPDDR4X. Even with 50% increase, LPDDR5 only provide extra 17 GB/s. Please compare to LPDDR6 and tell me how much difference in GB/s ? That is 100% extra

Of course that's always an open possibilty. But I am skeptical about it, especially with regards to Qualcomm doing so.

You see, these flagship 64-bit SoCs come integrated with cutting edge 5G modems. They take up about 15-20 mm² of die area.

Not all brands want to put 5G in their laptops. So the added cost of the 5g modem but it's redundancy when not used, is a waste of money. Hence why all Snapdragon 8cx chips and now the Snapdragon X Elite don't have integrated modems.

Qualcomm and Mediatek could disable 5G modem if they want. And do you think it will be cheaper for Qualcomm and Mediatek to design new SoC which support same memory bandwidth?

Plus X-Elite always has an option to add 5G modem, so Mediatek and Qualcomm with integrated modem is actually a plus ....

Man, you really want to argue for the sake of argument.

 

[FlameTail]

Man, you really want to argue for the sake of argument.

No, I am sorry, but it seems you being a bit
disingenuous with your arguments. To me, it appears you are overhyping LPDDR6.

But yes I'll stop the arguing, if you wish so.

 

[Glo.]

AMD's Speculation on LPDDR6 solution

Due to ever increasing memory bandwidth of LPDDR6, (Strix Point's die size is around 225mm2) AMD could switch to ARM platform in the future. It is game changer for AMD from technical AND business points of view. TLDR, please follow up in the following thread:

AMD's Future APU Gone ARM

AMD will likely be providing monolithics ARM SoC with 64-bit and 128-bit LPDDR6 support. Meanwhile, AMD will keep upgrading Sarlak's family as shown below:-

View attachment 95452

Last time, adroc said Sarlak's performance is about 7600M level. Based on memory bandwidth, yeah it is comparable. The only thing is RX7600M is build by N6 process with 28 CU @ 2.41GHz. Meanwhile, Sarlak's iGPU is having 40CU build by N3E process. Why do AMD need so many CU for RX7600M's performance?

My theory is AMD is planning to support LPDDR6 support on the same silicon. AMD could potentially bump the memory controller from 4.3 Gbps to 6.4 Gbps, then total memory bandwidth will increase to 410 GB/s.

If AMD is releasing Sarlak with LPDDR5x first, Sarlak6 will come one year later with 50% memory bandwidth improvement. In IT world, anything above 50% improvement within same interface is considered big upgrade.

However, if AMD straight away launch Sarlak with LPDDR6 support due to early availability, then we should be expecting three times bandwidth improvement.

Let's see how the thing turn out....

LPDDR6 is not coming before 2026. DDR6 is coming AFTER LPDDR6.

Strix Point Halo is coming next year, with DDR5 memory controller. Before LPDDR/DDR6 achieves 12800 MT/s it will take very long time before we see something like this on consumer products, most likely - 2028, at the earliest. So in what world would AMD implement LPDDR6 memory controller for Strix Point/Sarlak SOCs?



this is how memory speed progresses with time. When LPDDR6 will come to consumer market - it will NOT start at 12800, but at 9600., not bringing ANY benefit over LPDDR5x 9600.

 

[FlameTail]

this is how memory speed progresses with time. When LPDDR6 will come to consumer market - it will NOT start at 12800, but at 9600., not bringing ANY benefit over LPDDR5x 9600.

umm, i dont think it will start at 9600.

LPDDR5 started at 5500 when it debuted in 2020.

So since LPDDR6 is double that of LPDDR5, I assume the starting for LPDDR6 will be 11000.

 

[Doug S]

Clearly you don't know what you are talking related to LPDDR6. Are you even familiar with PC market to begin with?

Beside 50% improvement of memory bandwidth, I have listed down potential game changer related to LPDDR6 including Apple. Beside bandwidth related, game changer could mean big change in platform choice like AMD.

With Sarlak supporting 256-bit LPDDR6, AMD could finally has GPU performance similar to upcoming RDNA4. And do you even know about Sarlak or RDNA4?

Since you are familiar with Apple, 12GB LPDDR6 as standard could view as game changer cause Apple finally upgrade the RAM from 8GB to 12GB. As for future LPDDR6 memory configuration, Apple new memory interfaces will last for many generations.

If you think this is NOT game changer, please tell me what is your NOT game changer's configuration? I would love to hear about it.

Wow talk about stretching.

There is NOTHING about LPDDR6 that helps Apple upgrade RAM size. They could do that at any time they want, that does not depend on LPDDR6 in any way!

And why would their LPDDR6 interface "last for many generations"? Are you now claiming LPDDR6 is so great no one will have any incentive to ever use LPDDR6X or LPDDR7?

 

[FlameTail]

LPDDR4X- 4266
LPDDR5- 5500
LPDDR5- 6400
LPDDR5X- 7500
LPDDR5X- 8533
LPDDR5T- 9600
LPDDR6- 11000
LPDDR6- 12800
LPDDR6X- 15000
LPDDR6X- 17066
LPDDR6T- 19200
...

 

[FlameTail]

I have a small question about RAM (not about LPDDR6),

Is it possible to have a 3-factor memory size on a 2-factor memory bus?

3-factor memory sizes: 6gb, 12gb, 24gb, 48gb, etc...

2-factor memory sizes: 8gb, 16gb, 32gb, 64gb, etc...

3-factor bus widths: 96 bit, 192 bit, 384 bit, etc...

2-factor bus widths: 64 bit, 128 bit, 256 bit, etc...

We know a combination like 12 GB + 64 bit is possible (Look at all the smartphones).

But is a combination like 16 GB + 96 bit possible?

As far as I know, there are no devices with such combos.

 

[Glo.]

umm, i dont think it will start at 9600.

LPDDR5 started at 5500 when it debuted in 2020.

So since LPDDR6 is double that of LPDDR5, I assume the starting for LPDDR6 will be 11000.

I should have written DDR6 will start at 9600 instead of LPDDR, but everybody should get the point.

 

[Tigerick]

Vivo China have launched new flagship tablet Vivo Pad3 Pro with Dimensity 9300. The SoC is the same SoC as flagship phone SoC with 5G modem disabled. The specs of tablet are pretty impressive as shown below: -

• Mediatek Dimensity 9300 4 x Cortex-X4 + 4 x A720
• Immortallis G720 12-core with hardware ray tracing
• TSMC N4P process
• 16GB LPDDR5X + 512GB SSD @ CNY3999 (~$600)
• 13" 3,096 x 2,064 144Hz 3:2 LCD
• 66W Fast charging
• 11,500 mAh battery which is rated at up to 70 days of standby
• AOSP without Google

In fact, the specs are even better than Surface Pro 9 5G with Qualcomm SQ3 at half price. Better yet, upcoming D9400 will be built by N3E process which provides even better performance and with exclusivity agreement over with Qualcomm, Mediatek could just support WoA beginning from 2025.

And we might have another surprise incoming, ie. we might see D9400 supporting 64-bit LPDDR6 if the RAM arrives in early 2025 as shown below.

 

[Tigerick]

The slide from Canalys provide timeline regarding upcoming SoC launching information. As for any leaks, timing could change (Strix Point for example). I will list down some interesting tidbits below:

• Canalys estimated that Apple will launch M4 series in Q1 next year is much more interesting cause I speculated Apple will launch MacBook with LPDDR6 as early as possible. There is news about upcoming 8 Gen 4 supporting LPDDR6 which I think is a bit too early. Anyhow, Q1 2025 seems believable cause JEDEC will approve LPDDR6 standard in Q3 this year. This gives OEMs half a year to manufacture system with LPDDR6.
• @adroc_thurston said Sarlak is fixed, then why don't AMD launch it in Computex? Why wait until Q1 2025? As I speculated in the early thread, we see how the Sarlak go....
• X Elite with 8 cores might not be correct naming...the thing is the launching date is same as 8 Gen4, could X without Elite be using the same SoC as 8 Gen4??? And 8 cores SoC could be 2+6 Phoenix cores?

 

[Tigerick]

Walmart began selling MBA13 with M1 SoC @ $699. You could view this notebook as MacBook SE. Even though the notebook was launched three years ago, the specs are still pretty impressive compared to the rest of fanless notebook and tablet. And Apple know it, that's why Apple still selling it but not through official web site. At $699, even 8+256 configuration seems OK compared to others...

Surface Go 3 has not been updated for two years plus cause Intel's low power SoC has not improved much. The thing could change when NV launch their ARM SoC in 2025..I think Microsoft will use NV SoC in their Surface Go 4 at aggressive price point ($600 - $700).

NV using Intel 3 to manufacture ARM SoC with 64-bit LPDDR6 is a very strategy move from Jensen. Compared to TSMC, I believe IFS has ample capacity to support NV if NV want to expand production. And I think Jensen has aimed much higher volume on his returning SoC. Think Switch's SoC which is made by SF and think how many millions Nintendo has shipped with Tegra SoC....hoho I want to say NV's ARM SoC going to be Black Ship moment for consumer PC market, we shall see..