Discussion RDNA4 + CDNA3 Architectures Thread

[DisEnchantment]

With the GFX940 patches in full swing since first week of March, it is looking like MI300 is not far in the distant future!
Usually AMD takes around 3Qs to get the support in LLVM and amdgpu. Lately, since RDNA2 the window they push to add support for new devices is much reduced to prevent leaks.
But looking at the flurry of code in LLVM, it is a lot of commits. Maybe because US Govt is starting to prepare the SW environment for El Capitan (Maybe to avoid slow bring up situation like Frontier for example)

See here for the GFX940 specific commits

History for llvm/lib/Target/AMDGPU - llvm/llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. - History for llvm/lib/Target/AMDGPU - llvm/llvm-project

github.com

Or Phoronix

More AMD "GFX940" Enablement Work Landing In LLVM - Phoronix

www.phoronix.com

There is a lot more if you know whom to follow in LLVM review chains (before getting merged to github), but I am not going to link AMD employees.

I am starting to think MI300 will launch around the same time like Hopper probably only a couple of months later!
Although I believe Hopper had problems not having a host CPU capable of doing PCIe 5 in the very near future therefore it might have gotten pushed back a bit until SPR and Genoa arrives later in 2022.
If PVC slips again I believe MI300 could launch before it

This is nuts, MI100/200/300 cadence is impressive.



Previous thread on CDNA2 and RDNA3 here

Question - Speculation: RDNA3 + CDNA2 Architectures Thread

Man I have been dying to make this one for a while now. First rumours for RDNA3 are here so new thread time! Just going to start off with this one for now: kopite7kimi on Twitter: "@VideoCardz Ah, I mean a simple mcm design with 10240 cores is not enough. Because the lift from RDNA2 to RDNA3...

forums.anandtech.com

 

[igor_kavinski]

Here: https://www.tweaktown.com/news/9499...on-tech-specs-not-finalized-report/index.html

"The big feature that this system will support is Sony's own proprietary DLSS-like solution, where they use their own machine learning to improve images so they can run things at a really high resolution and really high frame rate. They would include their own hardware in the PS5 Pro to do this," Grubb said in a recent episode of Game Mess Decides.

"That's where the 2x hardware ray tracing acceleration comes into place, but they would be able to do even more than just better hardware raytracing."

So their custom RT algo combined with their upscaling tech would provide the boost higher than what's possible with RDNA3.

 

[TESKATLIPOKA]

It's not DirectX 12 RT with PS5. They must've implemented something proprietary and optimized to boost RT only for their platform.

Some form of (fake) frame generation is not really interesting and says nothing about RDNA4 capability.

Here: https://www.tweaktown.com/news/9499...on-tech-specs-not-finalized-report/index.html



So their custom RT algo combined with their upscaling tech would provide the boost higher than what's possible with RDNA3.

I don't think FPS would be much better than what AMD is offering with FSR3, but quality could(should) be better.

 

[exquisitechar]

I wouldn't expect remotely impressive RT performance from AMD until RDNA5. Really just hope they fix RDNA3's botched perf/power with RDNA4.

 

[igor_kavinski]

So their custom RT algo combined with their upscaling tech would provide the boost higher than what's possible with RDNA3.

A clue here: https://insider-gaming.com/playstation-5-pro-more-specs/

In addition: 30 WGPs running specialised BVH8 traversal shaders vs 18 WGPs running BVH4 tranversal shaders on the standard PlayStation 5.

It's using their proprietary SDK so not sure if these improvements can be seen on PC in 2024.

 

[SolidQ]

Interesting

 

[jpiniero]

Really just hope they fix RDNA3's botched perf/power with RDNA4.

Well.. I suppose the PS5 Pro could be designed to fit into the Slim's chasis (at the wall power for the entire system is roughly 200 W) but it seems they had to drop the max GPU frequency a tad compared to the 2.23 Ghz of the base model.

 

[MoogleW]

Let me get this right. We are moving from 36 to 60CU. The highest RT boost is 4X. So if PS5 pro is using RDNA 4 RT then I guess that means we can expect 'up to':

4X/(60/36) = 2.4X RT performance per CU in RDNA 4.
On average 1.8X in practice.

More optimistically for AMD, lte say due to clock speeds, the actual change resembles more of a move to a 7700XT GPU spec so 2.7X RT in special cases.

2X on average in demanding scenarios
1.5X in lighter scenarios

 

[SteinFG]

Let me get this right. We are moving from 36 to 60CU. The highest RT boost is 4X.

That's against regular PS5, wgich doesn't have Spectral SR I assume. The "RT boost" they're talking about is most likely a combination of RT per CU uplift, CU count uplift, and new upscaling software

 

[Kepler_L2]

That's against regular PS5, wgich doesn't have Spectral SR I assume. The "RT boost" they're talking about is most likely a combination of RT per CU uplift, CU count uplift, and new upscaling software

New upscaling isn't faster.

 

[igor_kavinski]

New upscaling isn't faster.

There isn't much information available on BVH8 but from what little I've been able to find, it allows lowering memory requirements and scales better but it's more cpu intensive? That might explain why Sony is able to implement it only in PS5 Pro with its faster CPU. How much of the RT perf increase is coming from switching to BVH8?

 

[Tuna-Fish]

There isn't much information available on BVH8 but from what little I've been able to find, it allows lowering memory requirements and scales better but it's more cpu intensive? That might explain why Sony is able to implement it only in PS5 Pro with its faster CPU. How much of the RT perf increase is coming from switching to BVH8?

Why would it be more CPU intensive? I guess there could be slightly more work building the tree when things move, but that's offset by the average walk becoming shorter? I would assume the acceleration structure depth mostly depends on what is cheap to implement on the GPU. You'd want each level of the structure to fit neatly into a cache line on the GPU, and if you don't have an special instruction to quickly pack bits you are probably limited to fairly inefficient representation. I don't know what information exactly needs to be fit in the structure, but at least there needs to be pointers for each child and a f32 for every plane that divides the bounding box. IIRC AMD GPUs use 64 byte lines, so 8 8-byte pointers are right out because they would take up the whole line. AMD's choice of BVH4 and Intel's choice of BVH6 probably reflects this, BVH6 sounds silly but you can pack 6 pointers, 3 f32's and 32 bits of additional data (some of it needed to select direction that the planes cut) neatly in 64 bytes.

If you do have some kind of special instruction that lets you very quickly pack and unpack bits for this purpose, you can probably do better than that. Since all the nodes are cache line aligned, you can cut 6 bits of each pointer from the low end, and if you are willing to limit address space to 57 bits (128PB, plenty enough for the foreseeable future), you can cut 7 bits from the high end, giving you enough space for 8 pointers, 3 f32:s and one byte left over for metadata.

I suspect the reason BVH8 is only available in later GPUs is that they provided hardware support for it, not with full walkers but with instructions that quickly extract the nth pointer from such a packed structure. Node traversal needs to be really fast and iirc shifts generally aren't on GPU, so you wouldn't want to try to implement that without help.

 

[cherullo]

They probably use a flattened structure, so there's no need for proper pointers, 4-byte indexes are more than enough.

And RDNA1 cache lines are 128 bytes:

https://gpuopen.com/wp-content/uploads/2019/08/RDNA_Architecture_public.pdf

 

[Tuna-Fish]

They probably use a flattened structure, so there's no need for proper pointers, 4-byte indexes are more than enough.

And RDNA1 cache lines are 128 bytes:

https://gpuopen.com/wp-content/uploads/2019/08/RDNA_Architecture_public.pdf

Thanks. Then I got nothing, I don't understand why you'd use such a deep and narrow structure. ray/box checks are cheap compared to the cost of cache misses.

 

[DisEnchantment]

Thanks. Then I got nothing, I don't understand why you'd use such a deep and narrow structure. ray/box checks are cheap compared to the cost of cache misses.

This patent below could help you with the box node compression

Bounding volume hierarchy box node compression - Advanced Micro Devices, Inc.

<div p-id="p-0001">A technique for performing ray tracing operations is provided. The technique includes combining one or more common exponent values of a compressed box node with one or more minimum

www.freepatentsonline.com

This patent below contains handling both BVH4 and BVH8.

VARIABLE WIDTH BOUNDING VOLUME HIERARCHY NODES - Advanced Micro Devices, Inc.

<div p-id="p-0001">A technique for performing ray tracing operations is provided. The technique includes processing small bounding box nodes in a box intersection test circuit to generate intersection

www.freepatentsonline.com

I think for prebuilt BVH trees performance gain won't be much. For runtime generated BVH trees it could be a lot of boost.
Cache and memory subsystem will be key.
For BVH4 it fetches two cache lines, for BVH8, it fetches single cache line.

7. The method of claim 1, further comprising fetching the small bounding box nodes from a cache by fetching two cache lines and discarding unused portions of the cache lines.
8. The method of claim 1, further comprising fetching the large bounding box nodes from a cache by fetching a cache line as the large bounding box node.

https://twitter.com/NIV_Anteru , who also presented the amazing workgraphs demo recently is inventor of these patents below for generating new kind of BVH trees

ACCELERATION STRUCTURES WITH DELTA INSTANCES

• From <https://www.freepatentsonline.com/y2023/0097562.html>

Reduction of data to be stored for a BVH node by representing the data of a box or triangle as a delta from a base node using smaller data types. This reduces the amount of data that has to be fetched from memory. The generation of the modified BVH can be done outside of the GPU

OVERLAY TREES FOR RAY TRACING

• From <https://www.freepatentsonline.com/y2023/0196669.html>
  
  • Same as above but in this case only the changed part of a BVH hierarchy is overlaid on top of a base BVH hierarchy

Will only help runtime generated trees it looks like to me

BOUNDING VOLUME HIERARCHY HAVING ORIENTED BOUNDING BOXES WITH QUANTIZED ROTATIONS
From <https://www.freepatentsonline.com/y2023/0099806.html>
TECHNIQUES FOR INTRODUCING ORIENTED BOUNDING BOXES INTO BOUNDING VOLUME HIERARCHY
From <https://www.freepatentsonline.com/y2023/0027725.html>
COMMON CIRCUITRY FOR TRIANGLE INTERSECTION AND INSTANCE TRANSFORMATION FOR RAY TRACING
From <https://www.freepatentsonline.com/y2023/0206541.html>
VOLUME INTERSECTION USING ROTATED BOUNDING VOLUMES
https://www.freepatentsonline.com/y2023/0410426.html

Updated way to perform intersection tests too with rotated boxes

Rotated Bounding Box

• Rotate Bounding Box during BVH building and then rotate Ray to match the bounding box
• Rotated bounding boxes improve performance because poorly rotated bounding box have more chances of hitting the box but not hitting the triangle inside

Poorly-fit bounding boxes can negatively impact performance because hits within poorly-fit bounding boxes that do not hit any underlying triangles are more common than hits within well-fit bounding boxes that do not hit any underlying triangles. The chance of a hit is directly related to the ratio of box volume to triangle surface area. Note that the two-dimensional diagram provided does not illustrate how much empty space there can be in a three-dimensional bounding box—there can be a much greater amount of such empty space in a three-dimensional bounding box. In addition, with a relatively large number of poorly fit bounding boxes, there is a greater chance that bounding boxes overlap (since bounding boxes must bound the interior geometry), which represents a degree of inefficiency. Hits within bounding boxes that do not hit any underlying triangles result in inefficiencies—it would be advantageous to stop traversal down a branch of a bounding volume hierarchy as early as possible if there are no triangles in that branch that are hit by the ray.

From <https://www.freepatentsonline.com/y2023/0099806.html>

• The ray is rotated before intersection test on a bounding box and the triangles inside within the intersection engine. The generation of the modified BVH can be done outside the GPU

I doubt PS5 will get all these with the weak CPU (if the BVH generation is not done on GPU)

 

[eek2121]

8800 class part (some people speculated otherwise). AMD Fixed clock issues plaguing RDNA3 (for RDNA4, not 3). > 50% perf uplift.

 

[igor_kavinski]

AMD Fixed clock issues plaguing RDNA3 (for RDNA4, not 3). > 50% perf uplift.

Rasterization or RT or both?

If that's rasterization, +50% puts the 8800 XT at close to 4090 1080p performance and almost 4080 performance at 4K.

 

[jpiniero]

8800 class part (some people speculated otherwise). AMD Fixed clock issues plaguing RDNA3 (for RDNA4, not 3). > 50% perf uplift.

I don't think the clock issue is as big as you think, unless you are thinking by 'fixed clocks' you mean 4+ Ghz.

 

[gdansk]

I assume the comparison was for 7800 XT where in many games (e.g. Cyberpunk) it's averaging 2350MHz which puts RDNA4 on the 3500 MHz hype train, not 4GHz.

 

[jpiniero]

I assume the comparison was for 7800 XT where in many games (e.g. Cyberpunk) it's averaging 2350MHz which puts RDNA4 on the 3500 MHz hype train, not 4GHz.

I was looking at the 3dmark data (of the 7900 XT), which while there is a huge spread... there were plenty that were hitting 2.8 if not a bit more. Plus the APUs can hit that high.

The issue might be more power consumption/AMD overvolting to maximize yield.

 

[MoogleW]

I don't think the clock issue is as big as you think, unless you are thinking by 'fixed clocks' you mean 4+ Ghz.

If 'fixed' means AMD clocks so high, on a node that promises FAR less clock improvements, AMD design team would be lightyears ahead of anyone else and I'm not convinced.

If there even is such a 'bug', then I would expect at MOST 3.2ghz clock, 30% higher than boost clock of 6700XT and over 40% boost clock of 6800XT in games. At least according to this.

AMD Radeon RX 6800 XT Specs

AMD Navi 21, 2250 MHz, 4608 Cores, 288 TMUs, 128 ROPs, 16384 MB GDDR6, 2000 MHz, 256 bit

www.techpowerup.com

AMD Radeon RX 6700 XT Specs

AMD Navi 22, 2581 MHz, 2560 Cores, 160 TMUs, 64 ROPs, 12288 MB GDDR6, 2000 MHz, 192 bit

www.techpowerup.com

 

[TESKATLIPOKA]

Even If RDNA4 or RDNA3.5 can clock at 3.2->3.5GHz, you still need to feed It.
Just look at the difference between 7700XT vs 7800XT. 6-7% in raw power, but thanks to the crippled memory subsystem you loose 15->19->22% depending on resolution.

 

[gdansk]

Even If RDNA4 or RDNA3.5 can clock at 3.2->3.5GHz, you still need to feed It.
Just look at the difference between 7700XT vs 7800XT. 6-7% in raw power, but thanks to the crippled memory subsystem you loose 15->19->22% depending on resolution.

Conversely, 7800XT has 44% more bandwidth but is only 15-22% faster.
Upgrade from 19.5gbps to 24gbps could be good enough.

 

[TESKATLIPOKA]

Conversely, 7800XT has 44% more bandwidth but is only 15-22% faster.
Upgrade from 19.5gbps to 24gbps could be good enough.

I disagree with you.
7800XT has higher BW than needed, increasing It from 19.5gbps to 24gbps wouldn't help unless you increase GPU clocks significantly.

P.S. this BW should be enough for ~3GHz and the extra 16MB for another couple of 100mhz.

 

[adroc_thurston]

7800XT has higher BW than needed, increasing It from 19.5gbps to 24gbps wouldn't help unless you increase GPU clocks significantly.

Yeap, out of all the parts only 7900GRE (40WGP@256b G6) is anywhere close to bandwidth limitations.
All N3x configs were sized for higher clocks.

 

[gdansk]

I'm not following. If the successor to 7800 XT is 3500MHz in games, then a higher speed GDDR6 will likely be sufficient. You think it won't be?