Putting the interconnects on top seems like a really nice way of doing that. The chips would obviously be design in a way that the toasty parts of GPU chiplets (CUs) and interconnects (L3) are not not under each-other.
If we examine the patent from AMD and cross reference with what kind of packaging TSMC (and we could even investigate the timeline) is offering it might be possible to make a reasonable explanation why the patent is how it is and why the previous patent could have been superseded.
One main problem is indeed heat transfer, and the main drawback of CoWoS and InFO (all other BE based stacking) is that there is a metallic layer as well and the chips are stacked together using Micro bumps. The issue with this is that there is a problem with heat transfer from one die to another across the microbumps. In addition to having to take care about different thermal coefficients of different materials.
Looking at the new patent for chiplet fabrication, there are no bumps/metallic layers between the two dies depicted which makes me believe this is probably FE based like SoIC
The FE based stacking make use of same material for the stacked dies and they have same thermal coefficient and the bonding layer allows for a better thermal transfer.
Only issue with this is that there are constraints in how the dies can be mixed and matched, but of course reaping all the benefits of chiplets when co designed properly.
In short, it seems to me the previous patent below uses CoWoS
Whereas the new patent uses SoIC
Read about advantages of SoIC vs CoWoS here
TL;DR; SoIC offers better thermal characteristics than CoWoS
Also I think FE actually is basically only the layers before any metal layers are done, not as described in the AT article.