Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[eek2121]

That article mentions only one patent, and it's the boring patent covering the possibility of hybrid cores posing as one. I think the author just took the Strix Point containing big.LITTLE rumor going around on Twitter at the time, looked up one patent and ran with that.

Personally I'm confident that AMD will do "hybrid" "cores".
- The OS and software won't see the additional "cores", that's what the patent in the article is about, transparent moving of a thread from one core to another hybrid one without software interaction.
- But the "core" won't even be complete on its own! That's the second, the promising patent covering this topic was about, catching illegal opcode exceptions and moving code to another core that can handle said opcode. This approach would allow to create very fast and efficient dumb cores that can speed up common simple code, with the usual fat core only having to handle all the more complex cases.

@DisEnchantment mentioned both patents back in June:
http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=threads/speculation-zen-4-epyc-4-genoa-ryzen-6000.2571425/post-40522899

I expanded on the latter patent back then which I still consider a big deal:
http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=threads/speculation-zen-4-epyc-4-genoa-ryzen-6000.2571425/post-40523434
I can imagine that one to be part of the excitement at AMD around Zen 5.

AMD has indicated pretty clearly that they have no plans for a hybrid approach. As they already have a much more efficient design than Intel, they really don’t need to go down that road.

Patents can be filed for “just in case” scenarios.

 

[moinmoin]

AMD has indicated pretty clearly that they have no plans for a hybrid approach. As they already have a much more efficient design than Intel, they really don’t need to go down that road.

Patents can be filed for “just in case” scenarios.

AMD has no interested in any big.LITTLE hybrid approach, and we won't ever see that from them. What the patents when combined describe is essentially extending existing cores with additional functionality that, when completed, would be able to form another core. But the very point is that they will never be completed and never be accessible as stand alone cores, it will just be additional functionality to relieve the rest of the core from lower level work.

This btw. also shows a path to seamlessly integrating Xilinx FPGA functionality as part of the cores without having to rely on software support for making use of that.

 

[eek2121]

AMD has no interested in any big.LITTLE hybrid approach, and we won't ever see that from them. What the patents when combined describe is essentially extending existing cores with additional functionality that, when completed, would be able to form another core. But the very point is that they will never be completed and never be accessible as stand alone cores, it will just be additional functionality to relieve the rest of the core from lower level work.

This btw. also shows a path to seamlessly integrating Xilinx FPGA functionality as part of the cores without having to rely on software support for making use of that.

I would never say “never”. If Intel really nailed an approach in a way that leaves AMD, they would adapt. That being said, I agree.

 

[DisEnchantment]

Long post, again!

If one looks at the changes in the cores from Zen to Zen 2 and the ones from Zen 2 to 3 one can notice that the latter makes mostly architectural changes while the former does mostly size changes (wider, larger, more, needing more die area). I'm expecting Zen 4 to follow the pattern of the former.

The rhythm seems to be:
- Ground up re-design, same node optimization. (~Zen, Zen 3)
- Same design optimized and extended to make good use of the additional area afforded by new smaller node. (Zen 2, Zen 4?)

That'd make Mike Clark's excitement about Zen 5 understandable as well considering that's the next ground up re-design in the queue, the first with AMD being the healthy company it is nowadays.

Btw.

New Zen gen only every 18 months confirmed. @DrMrLordX vindicated
(The interview is actually a little fuzzy on that since later on they talk about another three years later being Zen 8, not 7. But that's by Ian and Clark just seems to play along without really confirming or denying it.)

Zen4 and Zen5 should use the same packages. (Just like Zen...Zen3)

I agree, seems to be the case
It seems Zen4 will be a packaging innovation + process jump + core count increase (Server) with same Zen3 Architecture + extensions/improvements afforded by process. Zen 4 no wonder had the same family as Zen3.
Just like Zen2 was a packaging innovation + process jump + core count increase with same Zen1 Architecture + extensions/improvement afforded by process.
So Zen5 will be a new Architecture with same Zen4 packaging like Zen3 was. (Except that Zen5 will be on N3???, probably same IOD)

Zen4 and Zen5 should use the same packages. (Just like Zen...Zen3)
Most likely with the same CCD and IO die arrangements in the packages as well.

I would expect:

Zen4 ---> Zen5

(1) General use of PAM4 for the SERDES so:
- PCIe-5 --> PCI-6 doubles the bandwidth using the same frequency but 2 bit instead of 1 bit per clock edge.
- XGMI3 --> XGMI4 doubles the bandwidth between the IO die and the CCD's using the same number of pins

(2) Doubling the number of cores for each CCD's is enabled by doubling the SERDES bandwidth.
- 16 cores per CCD
- The same number of serdes IO lines
- L3 VCache in increments of 128 MB per die

View attachment 52057

I think you mean GMI not XGMI. CCDs don't have direct XGMI links

Also not sure PAM4 would be the best in terms of pJ/bit.
SDP-->CAKE-->IFOP.
Each IFOP has two unidirectional PHYs highly optimized for efficiency over very short distances.

Regarding stacking L3, I think AMD did talk about this as a future tech in ISSCC21. It changes the way one might visualize the floor plan of the core, by cutting so much trace lengths to the L3.


You probably took some inspiration from this patent too
20210312952 INTERCONNECT ARCHITECTURE FOR THREE-DIMENSIONAL PROCESSING SYSTEMS

https://www.freepatentsonline.com/y2021/0312952.html

What is strange though is that the SP5 socket is slightly thinner compared to SP3 in contrast to AM5 which got thicker compared to AM4

 

[maddie]

AMD has no interested in any big.LITTLE hybrid approach, and we won't ever see that from them. What the patents when combined describe is essentially extending existing cores with additional functionality that, when completed, would be able to form another core. But the very point is that they will never be completed and never be accessible as stand alone cores, it will just be additional functionality to relieve the rest of the core from lower level work.

This btw. also shows a path to seamlessly integrating Xilinx FPGA functionality as part of the cores without having to rely on software support for making use of that.

That is what I expect. Basically, a core within a core. Very fine grained power control needed.

 

[Harry_Wild]

https://www.digitaltrends.com/computing/amd-ryzen-6000-news-rumors-specs-release-date/

...As mentioned, the Ryzen 6000 chips are based on the Zen 4 architecture. This is a continuation of the Zen microarchitecture that AMD has been using since Ryzen 1000, but it uses a much smaller manufacturing process.

AMD has confirmed that Zen 4 will use a 5nm manufacturing process, and it will likely continue using chipmaker TSMC. Ryzen 5000 chips currently use TSMC’s 7nm manufacturing process.

AMD has confirmed that Zen 4 will use a 5nm manufacturing process, and it will likely continue using chipmaker TSMC. Ryzen 5000 chips currently use TSMC’s 7nm manufacturing process.
The 5nm node — known as N5 at TSMC — is said to offer a 15% boost in speed and 1.8X transistor density over N7. TSMC also says the node consumes 30% less power. That’s not to say Zen 4 will match those improvements, though. In reality, AMD can likely achieve a larger boost in speed through chip design.
The big deal is the 1.8X boost to transistor density. Although AMD hasn’t announced anything yet, Zen 4 chips will likely use a single-core design. That puts more focus on transistor density, essentially allowing AMD to squeeze more into the same die space.
These improvements are rumored to offer up to a 25% boost in single-core performance.

 

[Doug S]

The 5nm node — known as N5 at TSMC — is said to offer a 15% boost in speed and 1.8X transistor density over N7. TSMC also says the node consumes 30% less power. That’s not to say Zen 4 will match those improvements, though. In reality, AMD can likely achieve a larger boost in speed through chip design.
The big deal is the 1.8X boost to transistor density. Although AMD hasn’t announced anything yet, Zen 4 chips will likely use a single-core design. That puts more focus on transistor density, essentially allowing AMD to squeeze more into the same die space.
These improvements are rumored to offer up to a 25% boost in single-core performance.

Keep in mind you get EITHER 15% performance increase OR 30% less power. You don't get both at once.

The 1.8x transistor density is for logic. For cache it is only 1.3x. N3 is even worse for cache at only 1.2x! We won't see any real help with cache density until we see vertical GAA transistors (i.e. second gen GAA) which we won't see until whatever comes after N2 or maybe whatever comes after whatever comes after N2.

 

[leoneazzurro]

He is saying that BOTH improvement in process AND density will bring 25% more ST performance.

 

[Ajay]

We won't see any real help with cache density until we see vertical GAA transistors (i.e. second gen GAA) which we won't see until whatever comes after N2 or maybe whatever comes after whatever comes after N2.

Are you talking stacked nano-wire, or something else?

 

[Ajay]

Also not sure PAM4 would be the best in terms of pJ/bit.

PAM4 cuts jp/bit by 2, but the transceivers use a bit more power. OFC, signals over silicon bridge (or whatever) won't use nearly as much power as signal over substrate.

 

[Doug S]

Are you talking stacked nano-wire, or something else?

https://www.imec-int.com/en/imec-ma...al-nanowire-fet-enabler-of-highly-dense-srams

 

[DisEnchantment]

PAM4 cuts jp/bit by 2, but the transceivers use a bit more power. OFC, signals over silicon bridge (or whatever) won't use nearly as much power as signal over substrate.

PAM4 is too simple , check out the signaling scheme of the IFOP, it is not plain synchronous toggling of bits over the traces for which just moving to PAM4 will cut energy for data movement.

Infinity Fabric (IF) - AMD - WikiChip

Infinity Fabric (IF) is a proprietary system interconnect architecture that facilitates data and control transmission across all linked components. This architecture is utilized by AMD's recent microarchitectures for both CPU (i.e., Zen) and graphics (e.g., Vega), and any other additional...

en.wikichip.org

This was done by using a 32-bit low-swing single-ended data transmission with differential clocking which consumes roughly half the power of an equivalent differential drive. They utilize a zero-power driver state from the TX/RX impedance termination to the ground while the driver pull-up is disabled. This allows transmitting zeros with less power than transmitting ones which is also leveraged when the link is idle. Additionally inversion encoding was used to save another 10% average power per bit

There is a new updated extension filed to the original IFOP patent in fact which explains even more radical power conservation for such Xmtrs

https://www.freepatentsonline.com/y2021/0320672.html

You can bet they dare to add a second SDP most likely because they managed to bring down the pJ/bit.

 

[LightningZ71]

Keep in mind you get EITHER 15% performance increase OR 30% less power. You don't get both at once.

The 1.8x transistor density is for logic. For cache it is only 1.3x. N3 is even worse for cache at only 1.2x! We won't see any real help with cache density until we see vertical GAA transistors (i.e. second gen GAA) which we won't see until whatever comes after N2 or maybe whatever comes after whatever comes after N2.

Thus the move to stacking L3 cache. While the L2 caches can remain relatively small, the L3 will continue to be large. While cache scaling is lagging on new processes when using high performance libraries, they are doing better when using libraries optimized for L3. AMD's stacked cache die for Zen3d are using an optimized die and are getting nearly 2x density from it.

We'll be seeing a lot more stacking going forward because of the density scaling issues.

 

[Ajay]

https://www.imec-int.com/en/imec-ma...al-nanowire-fet-enabler-of-highly-dense-srams

Thx!

Very cool stuffs!

 

[Ajay]

PAM4 is too simple , check out the signaling scheme of the IFOP, it is not plain synchronous toggling of bits over the traces for which just moving to PAM4 will cut energy for data movement.

Infinity Fabric (IF) - AMD - WikiChip

Infinity Fabric (IF) is a proprietary system interconnect architecture that facilitates data and control transmission across all linked components. This architecture is utilized by AMD's recent microarchitectures for both CPU (i.e., Zen) and graphics (e.g., Vega), and any other additional...

en.wikichip.org

There is a new updated extension filed to the original IFOP patent in fact which explains even more radical power conservation for such Xmtrs

https://www.freepatentsonline.com/y2021/0320672.html

You can bet they dare to add a second SDP most likely because they managed to bring down the pJ/bit.

So, I've seen this a couple of times, but fail to see what the SDP is. Certainly, it's not about Bluetooth devices

 

[Doug S]

Thx!

Very cool stuffs!

I think about that diagram and wonder how many process steps they will have for two vertical gates stacked on top of each other and selectors underneath. Instead of 2-3 months from the first fab step to the wafer being finished we could see 4+ months. Yikes!

 

[Kedas]

I was thinking how AMD could have the same effect with 1 core as intel with P and E cores.
One group of 4 E cores with 4 thread takes the same die space as 1 P core. (intel)

Wouldn't AMD be able to switch between E and P mode if they can disable/enable STM4 per core and lower the max clocks?

We have been thinking about STM4 to get better performance but what if you use it as a low power mode...

I know you can't compare exactly 4 small cores with 4 threads to 1 core with 4 threads but the silicon area is about the same and if you design it with that goal mind...
Too soon for Zen4 probably, although lately AMD seems to have big surprises on presentations, no leaker knew. Maybe for Zen5.

 

[DrMrLordX]

@Kedas

Despite the prognostications of certain very stubborn past users of these forums, AMD has still shown no sign of adopting SMT4 at any point in the future.

 

[Abwx]

Dunno if it was posted but Hans de Vries came with this at TW :

https://twitter.com/x/status/1454025358022516736

 

[NostaSeronx]

... AMD has still shown no sign of adopting SMT4 at any point in the future.

Actually, they have shown wanting to adopt SMT8. However, they cite a paper that <200 physical registers = hard-limit of IPC gain to SMT4.

https://images.anandtech.com/doci/16214/Zen3_arch_13.jpg

192 registers.
&

200 registers.

- https://patents.google.com/patent/US20210096920A1 = Still in ungranted status
CCW control unit shows four threads.
- https://patents.google.com/patent/US11144353B2 = Granted
"Core may concurrently execute instructions of a number of threads such as, for example, between two and eight concurrently executing threads."

There is also Yilin Zhang at AMD with SMT4-aimed resource capping techniques in AMD Research side. Which is more orientated towards limited resource 4-thread SMT, rather excess resource 4-thread SMT.

Going through all the names does show they are working on "Next-generation x86 core", etc. So, it will pop up eventually, just not now. Current rumors deny Zen4/Zen5 supporting SMT4, but Zen6-Zen8 are still up for it.

 

[Hans de Vries]

There is no SMT4 in Genoa:

 

[soresu]

Going through all the names does show they are working on "Next-generation x86 core", etc. So, it will pop up eventually, just not now. Current rumors deny Zen4/Zen5 supporting SMT4, but Zen6-Zen8 are still up for it.

NOOOOOOO!!

Summon not the demon you fool!

 

[Mopetar]

NOOOOOOO!!

Summon not the demon you fool!

Uh... can demons summon themselves now or something?

You would need a massive number of registers for SMT4 though or there'd be little point of switching to threads that are so starved for registers that they have to utilize the stack to a significant degree.

 

[eek2121]

https://www.digitaltrends.com/computing/amd-ryzen-6000-news-rumors-specs-release-date/

...As mentioned, the Ryzen 6000 chips are based on the Zen 4 architecture. This is a continuation of the Zen microarchitecture that AMD has been using since Ryzen 1000, but it uses a much smaller manufacturing process.

AMD has confirmed that Zen 4 will use a 5nm manufacturing process, and it will likely continue using chipmaker TSMC. Ryzen 5000 chips currently use TSMC’s 7nm manufacturing process.

AMD has confirmed that Zen 4 will use a 5nm manufacturing process, and it will likely continue using chipmaker TSMC. Ryzen 5000 chips currently use TSMC’s 7nm manufacturing process.
The 5nm node — known as N5 at TSMC — is said to offer a 15% boost in speed and 1.8X transistor density over N7. TSMC also says the node consumes 30% less power. That’s not to say Zen 4 will match those improvements, though. In reality, AMD can likely achieve a larger boost in speed through chip design.
The big deal is the 1.8X boost to transistor density. Although AMD hasn’t announced anything yet, Zen 4 chips will likely use a single-core design. That puts more focus on transistor density, essentially allowing AMD to squeeze more into the same die space.
These improvements are rumored to offer up to a 25% boost in single-core performance.

Zen 4 will probably not be Ryzen 6000. I would be shocked if it were.

There is evidence that Rembrandt is Ryzen 7000, so many of us assume Zen3D and B2 stepping will be Ryzen 6000. Zen 4 and Rembrandt will likely be Ryzen 7000.

I guess we will see.

 

[soresu]

Zen 4 will probably not be Ryzen 6000. I would be shocked if it were.

There is evidence that Rembrandt is Ryzen 7000, so many of us assume Zen3D and B2 stepping will be Ryzen 6000. Zen 4 and Rembrandt will likely be Ryzen 7000.

I guess we will see.

Yes Zen 4/Raphael is likely Ryzen 7xxx on AM5.

Rembrandt could vert well be Ryzen 6xxx H/HX/G/U as it is due at the same time as Zen3D in the first half of next year.

For sure the jump from Vega to RDNA2 and a 50% CU count increase does warrant a serious jump in nomenclature, but I doubt that they would do this as they have seemingly transitioned to a more synergistic nomenclature across their respective CPU/APU lines so that customers are less confused about which SKU came out in which year vs the previous arrangement with APUs being named as if they were a year ahead.

More likely Phoenix will be the main monolithic Ryzen 7xxx APU if the rumours are correct and it shares Zen 4 cores with Raphael, I just hope it doesn't take as long for RDNA3 to filter into APUs as RDNA2 did.