Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[jpiniero]

Agreed. If AMD keeps the model range and numbering like it currently looks like I expect the MSRPs to be kept as well.

Expect a price hike. Given that Zen 3 is outselling Alder Lake in DIY, I don''t think they are too concerned about Intel.

It should be much easier to get OEMs to use it beyond gaming desktops with the included IGP. We'll see if that actually happens.

 

[Ajay]

Expect a price hike. Given that Zen 3 is outselling Alder Lake in DIY, I don''t think they are too concerned about Intel.

It should be much easier to get OEMs to use it beyond gaming desktops with the included IGP. We'll see if that actually happens.

I thought we'd be seeing a price hike as well. Rumor wise, it does depend on what is being presented. 5999 RMB is ~$900, but the trick is, does that include tax? If it does, then the actual price in the US should work out to ~$750 for a 7950X (which is suspiciously the same as the current gen's original cost ).

Whatever the price, the cost of 32GB of fast DDR5 and an enthusiast grade motherboard will cost more than the CPU. It will be less when B650 boards are out w/ slower DDR5 4800/5200 with slack timings, or if 16GB kits have higher availability.

 

[nicalandia]

I thought we'd be seeing a price hike as well. Rumor wise, it does depend on what is being presented. 5999 RMB is ~$900, but the trick is, does that include tax? If it does, then the actual price in the US should work out to ~$750 for a 7950X (which is suspiciously the same as the current gen's original cost ).

Whatever the price, the cost of 32GB of fast DDR5 and an enthusiast grade motherboard will cost more than the CPU. It will be less when B650 boards are out w/ slower DDR5 4800/5200 with slack timings, or if 16GB kits have higher availability.

How much for this combo?

7950X
32 GB of DDR5
Raid SSD
4080 Ti

 

[moinmoin]

I thought we'd be seeing a price hike as well. Rumor wise, it does depend on what is being presented. 5999 RMB is ~$900, but the trick is, does that include tax? If it does, then the actual price in the US should work out to ~$750 for a 7950X (which is suspiciously the same as the current gen's original cost ).

VAT in China is 13% so that would be closer to ~$800, a price hike of ~6%. In the past AMD liked to increase MSRP by IPC increase which would somewhat match in this case. We'll see.

 

[Mopetar]

I think for either AMD or Intel the bigger problem is how does a customer justify paying $300 for a 6core these days compared to the 12400 or 5600x's current prices at or below $200.

Who's going to pay the premium for a new board and DDR5 and plug a $200 CPU into it?

Adjust for inflation and the ~15% improvement makes $300 worth more than it might seem like at first.

 

[Ranulf]

Who's going to pay the premium for a new board and DDR5 and plug a $200 CPU into it?

Adjust for inflation and the ~15% improvement makes $300 worth more than it might seem like at first.

15% perf jump for 33% more money. Meh. Every generation its seems inflation is used as an excuse. This gen it might actually be true.

 

[jamescox]

Whatever.

The "AMD chiplet design" is an interposer connecting an IO die with 1 or more chiplets. If you want to include any sublayer of the chip and call that a chiplet, I guess. But there are many layers of varying materials that make up this unit many refer to as a chiplet.

Even if my point was strained because of improper usage of the term chiplet. It should be easy to understand. Anything outside what I call a chiplet that has to go over infinity fabric really doesn't fit in the hierarchy of latency and bandwidth.

I was just trying to understand what you are talking about. Being pedantic, but It is a stretch to call AMD’s current “chiplet design” an interposer. The chips do not sit on a silicon interposer. It is just a little PCB with SerDes infinity fabric routed through it. It technically could be called an “interposer” but we generally wouldn’t refer to a DRAM module as an interposer, but it really isn’t that much different from Zen 2 and probably Zen 3 packages. They may have some RDL and such advanced packaging tech, but there are no silicon bridges or silicon interposers involved. Zen 4 may have some special sauce in the packaging tech though.

I don’t think cache chips are that unlikely. In fact, if Global Foundries ends up making HBM-type memory for AMD, I would wonder if they will include some special sauce rather than standard HBM. Putting an SRAM cache die at the bottom of the stack or some kind of processor in memory thing would be interesting. It is possible that the Zen 4 refresh of Bergamo will do away with SerDes based, on package IFOP connections and use silicon bridges instead or some combination. Some of the GPU rumors seem to indicate two gpu chips connected together with silicon bridges and HBM also connected with silicon bridges. Then SerDes IFOP may be used to connect multiple of these modules together. Bergamo or the GPUs could get infinity cache chips connected by silicon bridges. L4 for Bergamo could be done with silicon bridges but they could have L4 on the IO die for Bergamo rather than a separate chip. They may still call that infinity fabric or infinity architecture connected since it would be the same, except with the SerDes ripped out. They are probably more likely to use 3D stacked cache, whether under or over, rather than separate chips with silicon bridges. The chips stacked underneath may not be SoIC though. You can still get thousands of bits wide interfaces for micro-bump style stacking. That would probably be sufficient for GPU caches and L4 caches. Probably not for L3 though. I thought it might be one giant base die, but then that would have issues with passing power up through the stack. Using some smaller embedded cache chips and EFB style stacking would allow directly powering the compute die without going through TSVs. This type of stacking would also allow the cache chips to be made elsewhere just like HBM can be made at other companies. I don’t how dense Global Foundries processes are for caches though.

Anyway, I don’t think we have had any infinity fabric attached SRAM, other than something that is in the caches of another chiplet, so saying they aren’t going to do that doesn’t really make much sense, hence the confusion.

 

[jamescox]

The "AMD chiplet design" is an interposer connecting an IO die with 1 or more chiplets.

I think "One "AMD chiplet design" is an interposer connecting an IO die with 1 or more chiplets." might be accurate. Anything fabbed as a unique part and then "glued" together with others can be called a chiplet.

“Glued together” is marketing speak. AMD’s designs have, as far as know, been just MCMs with chips. The current AMD design isn’t exactly new, it is kind of just a smaller form factor. For decades, a cpu just connected to a bus with the chipset. It did not have any memory controllers or IO of it’s own. This is actually quite similar to current CPU “chiplets”. AMD did break new ground in 1999 because they switched away from using a shared bus to using a point to point link to each cpu:

AMD Athlon

www.anandtech.com

Previously, dual socket systems had the chipset and the CPUs all siting on a shared bus. The diagram in the link, at a high level, looks like a 5950x. Two cpu chips and one “IO die” connected by bi-directional point to point links. It is shrunk to fit on one little package for the 5950x rather than being on the mother board, but the basic system diagram is the same. After that, they moved the memory controller on die and put point to point links on the CPUs themselves. Having the memory controller on die reduces latency, but part of the reason for moving to this distributed system is that a central IO die got unmanageable at the time. They could also scale memory with the number of cpu cores. If you put 4 sockets on the board and needed bi-directional, point to point links, then the chipset would have way to many pins. It is probably not really a problem with todays technology but over 20 years ago it would have been very expensive, if it was possible. Having the point to point links on the cpu allowed them to connect 4 or more sockets together with no, so called, “glue”. What did a 4 socket Opteron system look like? At a high level, it looks almost exactly like Zen 1; 4 cpu die with serial, packetized, point to point links, just all on one MCM with Epyc 7000. It is great that AMD realized that they could do MCMs and have it perform well compared to monolithic chips before going all of the way to stacked 2.5 and 3D devices. Intel seems to have been planning on going to stacked devices eventually, without doing an MCM device with SerDes connections, but that doesn’t seem to have worked well.

I don’t mind them calling them chiplets, but what is the difference between the CPUs from over 20 years ago? The cpu in both cases is still a separate chip with no memory controllers or IO. Should they have been called chiplets in an MCM? Probably not. Chiplet probably should have been left to stacked devices. MCMs aren’t new either. IBM made MCMs a long time ago. I think the power 5 MCM is still bigger than even Genoa. It had 4 CPU die and 4 cache chips.

 

[HurleyBird]

Who's going to pay the premium for a new board and DDR5 and plug a $200 CPU into it?

Someone who has an older system, needs something now, but also intends to upgrade to Zen 5.

 

[RnR_au]

Someone who has an older system, needs something now, but also intends to upgrade to Zen 5.

Yeah someone like me... still on AM3+ for my little gaming system. Fortnite + Destiny 2 will get some nice gains regardless of the cpu I put in there.

 

[biostud]

Yeah someone like me... still on AM3+ for my little gaming system. Fortnite + Destiny 2 will get some nice gains regardless of the cpu I put in there.

Yup, I know the feeling X99 showing its age.

 

[DrMrLordX]

sorry, I'm not clear enough, what shocking me is if the naming scheme and core count is the same, means AMD don't care about the competition of big+little.

The 7950X should hold up pretty well against Raptor Lake. We also haven't seen Raphael-X yet, which may follow up pretty quickly. AMD can sit on that as a backup in case Raptor gets to be a problem. And that's just desktop.

 

[Ajay]

VAT in China is 13% so that would be closer to ~$800, a price hike of ~6%. In the past AMD liked to increase MSRP by IPC increase which would somewhat match in this case. We'll see.

Ugh.. thanks, I thought it was 17% or 18%.

 

[Ajay]

How much for this combo?

7950X
32 GB of DDR5
Raid SSD
4080 Ti

Pfft, newb . No idea what a 4080 Ti will cost. Gen5 PCIe for RAID?

 

[Timmah!]

How much for this combo?

7950X
32 GB of DDR5
Raid SSD
4080 Ti

I am looking for something similar:

7950x
64GB of DDR5
2x M2 1TB SSDs, one for system, other for games, so no raid, additionally will keep host of my disks from current rig (Samsung 960 Evo, another SSD i keep some work stuff on, 3x WD HDDs)
2 x 4090 (or single one and keep 3090)

the only bummer is the lack of 24 core, i truly wanted that, hopefully eventual one in a year or 2 will fit the socket

 

[Schmide]

I was just trying to understand what you are talking about. Being pedantic, but It is a stretch to call AMD’s current “chiplet design” an interposer. The chips do not sit on a silicon interposer. It is just a little PCB with SerDes infinity fabric routed through it. It technically could be called an “interposer” but we generally wouldn’t refer to a DRAM module as an interposer, but it really isn’t that much different from Zen 2 and probably Zen 3 packages. They may have some RDL and such advanced packaging tech, but there are no silicon bridges or silicon interposers involved. Zen 4 may have some special sauce in the packaging tech though.

I don’t think cache chips are that unlikely. In fact, if Global Foundries ends up making HBM-type memory for AMD, I would wonder if they will include some special sauce rather than standard HBM. Putting an SRAM cache die at the bottom of the stack or some kind of processor in memory thing would be interesting. It is possible that the Zen 4 refresh of Bergamo will do away with SerDes based, on package IFOP connections and use silicon bridges instead or some combination. Some of the GPU rumors seem to indicate two gpu chips connected together with silicon bridges and HBM also connected with silicon bridges. Then SerDes IFOP may be used to connect multiple of these modules together. Bergamo or the GPUs could get infinity cache chips connected by silicon bridges. L4 for Bergamo could be done with silicon bridges but they could have L4 on the IO die for Bergamo rather than a separate chip. They may still call that infinity fabric or infinity architecture connected since it would be the same, except with the SerDes ripped out. They are probably more likely to use 3D stacked cache, whether under or over, rather than separate chips with silicon bridges. The chips stacked underneath may not be SoIC though. You can still get thousands of bits wide interfaces for micro-bump style stacking. That would probably be sufficient for GPU caches and L4 caches. Probably not for L3 though. I thought it might be one giant base die, but then that would have issues with passing power up through the stack. Using some smaller embedded cache chips and EFB style stacking would allow directly powering the compute die without going through TSVs. This type of stacking would also allow the cache chips to be made elsewhere just like HBM can be made at other companies. I don’t how dense Global Foundries processes are for caches though.

Anyway, I don’t think we have had any infinity fabric attached SRAM, other than something that is in the caches of another chiplet, so saying they aren’t going to do that doesn’t really make much sense, hence the confusion.

Interposer - means to route between places. Latin interponere - inter (between) - ponere (put in place). Yes I looked this up.

I agree that it takes on extra contextual meaning when a custom bridge (silicon interposer/ passive / active / 2.5d / 3d ) is used and maybe it was a stretch to call amd's MCM an interposer. (can we call Foveros a chiplet? Asking for a friend)

I'm glad you mentioned the SerDes (serializer/deserializer). This is the bottleneck I was eluding to when expressing my opinion that stand alone cache chips do not really fit in the memory hierarchy. Uniquely this responsibility, at least in the new server chips (MI250), seems to be shifting to the GPUs. There are a whole bunch of network processors that seem to use GPU technology to accelerate things but that is a whole other topic to dive into.

I don't remember where I heard this about Bergamo and it kind of reminds me of IBM's unique cache sharing technique where they optimized the sharing and usage of cache between neighboring units. Bergamo was/is rumored to have one set of processors with stacked cache that runs less aggressively and one without that that runs at full speed. Maybe there will be some special interconnect similar to IBM's method to integrate the extra cache on the full speed processors.

 

[TESKATLIPOKA]

How much for this combo?

7950X
32 GB of DDR5
Raid SSD
4080 Ti

I think one sold kidney should be enough.

 

[Abwx]

the only bummer is the lack of 24 core, i truly wanted that, hopefully eventual one in a year or 2 will fit the socket

16 Zen 4 cores amount to 21.6 Zen 3 cores, so that s about it...

 

[Timmah!]

16 Zen 4 cores amount to 21.6 Zen 3 cores, so that s about it...

Yeah, but still amounts to 8 less than 24 Zen4 cores, which is what i was hoping for

 

[Mopetar]

Someone who has an older system, needs something now, but also intends to upgrade to Zen 5.

Unless it predates Zen itself you'd likely be better off upgrading to a newer version of Zen and getting on AM5 later when the prices become a lot more normal.

 

[HurleyBird]

Unless it predates Zen itself you'd likely be better off upgrading to a newer version of Zen and getting on AM5 later when the prices become a lot more normal.

Agreed, and probably get faster memory and a better motherboard when you do it. If you're on AM4.

 

[rtxtwt]

No doubt in my mind that the 7600X will beat the 12600K at gaming and in MT performance.

Maybe you are right. Some local sellers receive order from AMD, to clear their Zen3 equipments as fast as possible, these seller's tone hinting the performance impact would be large enough to fully make Zen3 obsolete. Now I would not be surprised if 7600X price against 12600k. Maybe I worry too much after seeing the identical naming scheme and core counts.

I thought we'd be seeing a price hike as well. Rumor wise, it does depend on what is being presented. 5999 RMB is ~$900, but the trick is, does that include tax? If it does, then the actual price in the US should work out to ~$750 for a 7950X (which is suspiciously the same as the current gen's original cost ).

Not include tax maybe. If these rumored price is correct I guess these price is not even a price hike, it's just a copy pasta from Zen3's MSRP price. 7600X is more expensive than 12600k and no DDR4 support with X670 mobo and no B650 at day 1.
Dunno what's going wrong here. But the rumor is rumor still.

 

[DrMrLordX]

I'm surprised there will be a 7600X at all.

 

[biostud]

I'm surprised there will be a 7600X at all.

There will always be some faulty chiplets or some that do not clock so high, those can be used in 7600X.

But sure they have to priced aggressively, if you would choose one over a 5800x.

 

[Kedas]

Since Zen4c is on 4nm and Phoenix Point is on 4nm.
Doesn't that mean that it's likely that the mobile market wil get Zen4c instead of Zen4?