Technically CCDs diverged already with Bergamo and the Zen 4c CCD.
Indications so far are that with Zen 5 DT is going to use mobile dies, no longer server dies (which may also mean no more X3D variants, which again would mean the Zen 5 core on its own is required to offer sufficient performance increase etc. pp.).
I wouldn't say that as they started selling X3D chips in mobile, and I believe X3D helped those chips be tops in perf/W in gaming. But if base Zen 5 offers high levels of gaming performance they likely won't need X3D and might hold off until they make other packaging changes that are rumored to be coming in Zen 6. I kinda wondered if the large cache might make more sense on the IOD. The changes with Zen 4c seem almost like its foretelling how AMD might keep increasing core counts by reducing cache at CCD but still maintaining performance. Plus in less highly threaded workloads, it could be fewer cores getting larger cache, but without having the scheduling issues that putting it on one of the CCDs does (so maybe could distribute the workload, i.e. each CCD has half the cores working so instead of all 8 on one CCD it'd be 4/4 but still 8 cores, which could help with heat distribution). Guess that won't matter as much if Zen 5 is going to 16 core CCDs (and its still supposed to top out at 16 cores).
Which, consumer side, I'd think X3D would make more sense for say putting on an IOD that's bridging CPU and GPU chiplets, where its a large buffer for unified memory (where it could help boost DDR bandwidth, or help with the latency of GDDR, or maybe to simplify HBM stacks where you go with fewer stacks - and thus less complexity - with the cache directing things to the processing chiplets), and basically combine idea behind InfinityCache and X3D, but shared so lowering the overall cost, but making it so either could leverage its benefits depending on the workload.
If Zen5 DT will use mobile dies perhaps we can also expect lower power consumption at idle, since that is important for laptop CPUs.
Sounds like that might have to wait. The issue there is the uncore which seems like it got less of the focus in Zen 5, or perhaps more that to facilitate the performance uplift it will be performance focused. Rumors suggest quite a lot of changes coming in Zen 6 (packaging and uncore/fabric stuff). As long as Zen 5 maintains ability to overall be efficient (similar to Zen 4 where it could do low TDP and be efficient, at least the monolithic mobile chips; but also could push higher, where it traded that idle efficiency for "performance efficiency" where it just offers good perf/W when being utilized). Which, if they can expand the top end even more that'd be fine, where they enable more performance if you have the power delivery and ability to dissipate the heat (just hoping its not Intel levels unless performance scales up there).
That's fabric power.
Not changing much until Medusa.
It's the exact same cIOD.
No, no, yes, a bit.
Ah. Not surprising. Really likely not a big deal as overall Zen 4 was still pretty efficient and using hibernate would be more feasible than idle for a computer. The 8cx Gen 3 Windows tablet I got doesn't have hibernate as an option but basically more or less hibernates and it really sips power (I think I went a couple of weeks without using it - didn't shutdown - and it had lost barely any battery life like maybe 5% during that span; I'd guess an AMD laptop in Hibernate could offer similar).
Big changes are coming then? Rumors saying packaging changes and I saw some other saying new high bandwidth interconnect (assume that's InfinityFabric level, not like PCIe/etc).
Oh that's right. Had to look up the capabilities. Seems like it should still be workable without needing a dGPU for normal tasks, and does have AV1 decode at least (especially since I think you've said encoding quality isn't really a major focus of AMD's video processing blocks; plus that's what the powerful CPU is for). Hmm, did see mention of it being able to output display via TB. I was wondering if we might would be able to see TB5 support (one of the reasons I asked about new chipset; but I think TB5 would still probably need a dedicated controller chip anyway; I forget how it changed, was it TB3 went royalty free but TB4 required a chip, except for some Intel which integrated it?). Not really directed at you but seems most of the eGPU crowd seems to favor Oculink over TB, wonder if it was being updated; might be moot as more of the mini-PCs seem like they're starting to integrate full on PCIe x16 ports).
Makes sense (now if mobo makers, cases, and other would go heavier on USB-C ports than USB-A). It should have same PCIe lanes to Zen 4 (24 PCIe 5? Er, no 28!) I'm assuming?