Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Abwx]

No, as usual you understand very little of how process nodes can be tweaked to account for target PPA which is variable based on the design under consideration.

An A78 shrunk from N5 to N4 will certainly not be the same as a Zen 5 shrunk from N5 to N4 as they are vastly different PPA targets.

I guess that it s you who dont understand, when you shrink a core to a smaller but comparable process then it s just the curve that is translated in a graph, FI if a Cortex fabbed with N5 run a 2GHz and consume 0.25W then a shrink with a process that use 20% lower power/isofrequency will yield 0.2W/2GHz, likewise if a X86 core use 20W/5GHz then with the new process it will use 16W/5GHz.

What you dont understand is that the parasitic and strain capacitances will be the same for both x86 and Cortex cores, guess that you are so afraid that AMD can make a big improvement that you are left inventing technical impossibilities, and while i m talking process characteristics you re talking exorcism with some kind of vade retro AMD awe.

 

[tamz_msc]

I guess that it s you who dont understand, when you shrink a core to a smaller but comparable process then it s just the curve that is translated in a graph, FI if a Cortex fabbed with N5 run a 2GHz and consume 0.25W then a shrink with a process that use 20% lower power/isofrequency will yield 0.2W/2GHz, likewise if a X86 core use 20W/5GHz then with the new process it will use 16W/5GHz.

Power-frequency scaling is dependent on the design. A node to node shrink of an x86 core will give different PPA than a node to node shrink of an arm core.

 

[Abwx]

Power-frequency scaling is dependent on the design. A node to node shrink of an x86 core will give different PPA than a node to node shrink of an arm core.

Not at all, and that s the prove that you understand jack to transistors physics, PPA will be strictly the same, otherwise why would TSMC publish characteristics if they couldnt reproduce them with their customers products..?.

What would be the meaning of those numbers , tell us :

TSMC Details N4X Process for HPC: Extreme Performance at Minimum Leakage

www.anandtech.com

So you are saying that TSMC cant guarantee those numbers with anything other than their tests chips..?..
Are you that dense..?..

 

[Fjodor2001]

IPC isn't free, you're paying in area and power.

So are we expecting MT perf increase to be worse than ST perf increase, since for MT it will hit the power limit preventing further perf increase?

 

[tamz_msc]

So you are saying that TSMC cant guarantee those numbers with anything other than their tests chips..?..

A14 = 11.8 billion xtors 88 mm2 die size = 134 MTr/mm2 (N5)

A13 = 8.5 billion xtors 99 mm^2 die size = 85.6 MTr/mm2 (N7P)

Density increase = 1.57x

Which if my math is not wrong is lesser than 1.8x.

 

[adroc_thurston]

So are we expecting MT perf increase to be worse than ST perf increase

That's how it always goes, kiddo!

since for MT it will hit the power limit preventing further perf increase?

Socket-level per-thread perf bump is always lower than the 1t bump.

 

[Fjodor2001]

That's how it always goes, kiddo!

Socket-level per-thread perf bump is always lower than the 1t bump.

So what MT perf increase can be expected, going from 7950X or 7950X3D to corresponding Zen5 16C equivalents?

And what about perf/watt improvement for MT workloads? How much will that increase?

 

[Doug S]

A14 = 11.8 billion xtors 88 mm2 die size = 134 MTr/mm2 (N5)

A13 = 8.5 billion xtors 99 mm^2 die size = 85.6 MTr/mm2 (N7P)View attachment 96050

Density increase = 1.57x

Which if my math is not wrong is lesser than 1.8x.

You didn't read the table you posted. It says "logic area", while a real SoC includes transistors other than logic such as cache (leaving out the other categories that also aren't logic but maybe don't scale as poorly as cache)

 

[Abwx]

A14 = 11.8 billion xtors 88 mm2 die size = 134 MTr/mm2 (N5)

A13 = 8.5 billion xtors 99 mm^2 die size = 85.6 MTr/mm2 (N7P)View attachment 96050

Density increase = 1.57x

Which if my math is not wrong is lesser than 1.8x.

We re talking of PPA, you are just changing the goal posts, as if density has something to do with PPA, it took you all this time to find such a poor straw.?..

 

[H433x0n]

Unhappy with Cinebench speculation?
Then let me show you some happy data?

9950X

GeekBench 6
single 3628 more than 23868

GeekBench 5
single 2715 more than 27712

(Only test data, does not represent the final result)

If that’s a legit score that’d be a bad result since a 7950X will regularly score 3000-3200 and a 13900K will usually get a score in the range of 3100-3300.

A 30% 1T increase would mean a score >=4000.

 

[tamz_msc]

You didn't read the table you posted. It says "logic area", while a real SoC includes transistors other than logic such as cache (leaving out the other categories that also aren't logic but maybe don't scale as poorly as cache)

A14 big core = 2.1 mm2
A13 big core = 2.61 mm2

Please tell me where the 1.8x logic density increase is in the actual chips?

We re talking of PPA, you are just changing the goal posts, as if density has something to do with PPA, it took you all this time to find such a poor straw.?..

Yes. A13 and A14 are almost the same architecture as far as the CPU is concerned. As demonstrated above, the logic density increase is nowhere near what TSMC advertises - because they typically have an old arm core as the reference.

And frequency/power claims are even more misleading. They typically refer to a simple ring oscillator, let alone a basic CPU.

It's not my problem if you are clueless, which isn't surprising.

 

[tamz_msc]

If that’s a legit score that’d be a bad result since a 7950X will regularly score 3000-3200 and a 13900K will usually get a score in the range of 3100-3300.

A 30% 1T increase would mean a score >=4000.

I think they guy was joking. Apparently not.

If the leak is right, then 3600 score is nowhere close to reflecting a 40% core for core perf increase.

 

[Timorous]

Pretty sure the 40% refers to spec int 2017 ST only.

 

[Fjodor2001]

Pretty sure the 40% refers to spec int 2017 ST only.

So 40+ % perf increase in that benchmark, but only 3628/3100 => ~20 % in GB6 compared to 7950X?

And also, if 13900K is 3300 in GB6 like @H433x0n said it would mean 9950X is only ~10% better than that.

 

[tamz_msc]

Pretty sure the 40% refers to spec int 2017 ST only.

Which should correlate well with Geekbench 6 1T.

 

[Timorous]

So 40+ % perf increase in that benchmark, but only 3628/3100 => ~20 % in GB6 compared to 7950X?

And also, if 13900K is 3300 in GB6 like @H433x0n said it would mean 9950X is only ~10% better than that.

Which should correlate well with Geekbench 6 1T.

I am just pointing out a factual statement, if it should or should not correlate is of no relevance to ensuring the accuracy of the claim which was always centred around SIR2017 ST, whether that be the 32% IPC claim or the 40% performance claim.

What I can see happening by certain posters is the performance delta differing in CB / GB / CPU-Z and them using that to go see, the 40% was BS when the claim was always SIR2017 ST. If SIR2017 ST has a smaller performance bump than claimed sure, have at it but CB/ GB / CPU-Z are no the same as SIR2017 ST so don't conflate them.

 

[tamz_msc]

I am just pointing out a factual statement, if it should or should not correlate is of no relevance to ensuring the accuracy of the claim which was always centred around SIR2017 ST, whether that be the 32% IPC claim or the 40% performance claim.

What I can see happening by certain posters is the performance delta differing in CB / GB / CPU-Z and them using that to go see, the 40% was BS when the claim was always SIR2017 ST. If SIR2017 ST has a smaller performance bump than claimed sure, have at it but CB/ GB / CPU-Z are no the same as SIR2017 ST so don't conflate them.

What I'm implying is that SPECint_rate_2017 1T and Geekbench 6 ST correlating 1:1 means that either 40% performance gain over Zen 4 is untrue or that the ES leak showing a score of 3600 in ST is made up.

 

[Fjodor2001]

CB/ GB / CPU-Z are no the same as SIR2017 ST so don't conflate them

So the conclusion is that 40+ % in SIR2017 ST, and ~20% vs 7950X & ~10% vs 13900K in GB6, can both be valid since what the benchmarks measure differs so much?

Then the question is what benchmark to focus on. Or perhaps better look at an average of the different benchmarks, instead of just cherry-picking one of them.

 

[Abwx]

You didn't read the table you posted. It says "logic area", while a real SoC includes transistors other than logic such as cache (leaving out the other categories that also aren't logic but maybe don't scale as poorly as cache)

How could one read accurately when he s so busy finding anything he can to convince himself that AMD wont achieve what he fear the most, that is, that Intel could be trounced for good.

That s no more a technicaly motivated debate but some kind of irrational discussion with one in need of some exorcism against his own fears.

Anyway yet another good laugh, at least that s some kind of entertaining.

A14 big core = 2.1 mm2
A13 big core = 2.61 mm2

Please tell me where the 1.8x logic density increase is in the actual chips?


Yes. A13 and A14 are almost the same architecture as far as the CPU is concerned. As demonstrated above, the logic density increase is nowhere near what TSMC advertises - because they typically have an old arm core as the reference.

And frequency/power claims are even more misleading. They typically refer to a simple ring oscillator, let alone a basic CPU.

It's not my problem if you are clueless, which isn't surprising.

Lol...

They use basic CPUs from ARM, generaly a A78.

They add several ring oscillators that are of course not connected to the CPU, that s basic circuits but they allow to have an accurate modelisation of the process capabilities, namely transmission delay and the transistors impulse response, after wich the impulse response, wich is the time domain behaviour, allow to extract the transfert function wich is mapped in the frequency domain by using a simple Laplace transform, but i guess that you already knew all this, isnt it...

And you re talking of other people as being cluless..?.
That is, you re trying to bluff people in enginering matters.?

I m about sure that you didnt understand jack about what i m talking about, and yet, that s 18 years old EE students level, you could try at WCCF Tech forum, though, that could work there, eventually.

 

[Timorous]

What I'm implying is that SPECint_rate_2017 1T and Geekbench 6 ST correlating 1:1 means that either 40% performance gain over Zen 4 is untrue or that the ES leak showing a score of 3600 in ST is made up.

Or the ES is clock / power limited in someway that would not apply to a retail unit as a 3rd option. We will know more when we get details.

So the conclusion is that 40+ % in SIR2017 ST, and ~20% vs 7950X & ~10% vs 13900K in GB6, can both be valid since what the benchmarks measure differs so much?

Then the question is what benchmark to focus on. Or perhaps better look at an average of the different benchmarks, instead of just cherry-picking one of them.

Focus on the ones that matter to your use case. For me that will be gaming so even if SIR 2017 ST does see a 40% uplift if that does not translate to the games I play (assuming they get tested) it is mostly irrelevant from a purchasing POV. The only thing it will determine is if those making that claim are accurate or not.

 

[Fjodor2001]

Ok, well if SIR 2017 ST turns out to be a cherry-picked benchmark at 40% and other benchmarks are at 10-20% perf improvement compared to 7950X and 13900K, then I don’t see how AMD will be able to charge $999 for 9950X.

Especially since MT perf improvement will be less than for ST according to redacted, and the main benefit with the 16C in 9950X over 8C variants is the MT perf.

Tagging people is fine. Calling them out is not. Put them on ignore if they annoy or otherwise upset you.
-CPU Mod DAPUNISHER

 

[tamz_msc]

Or the ES is clock / power limited in someway that would not apply to a retail unit as a 3rd option. We will know more when we get details.

This was in January 2022.

AMD demonstrates its next-gen Zen4 Ryzen 7000 CPU in Halo Infinite with all-core frequency of 5GHz - VideoCardz.com

Ryzen 7000 is hitting 5.0 GHz on all cores, claims AMD During its 2022 Product Premiere AMD demonstrated its next-gen processor with a short gameplay video. AMD not only confirmed the leaks featuring a unique AM5 CPU integrated heat spreader design but also confirmed it will be the first...

videocardz.com

Zen 4 launched in September 2022.

The Zen 5 GB6 leak was from November 2023.

Given AMD's history of leaks and teasers, I don't think there is very strong evidence to believe that the ES was running at clocks very far from final targets.

 

[FlameTail]

Well yeah Geekbench and SPEC tend to correlate pretty well.

So Zen 5 has only a 15% increase in Geekbench but a 40% increase in SIR2017?

 

[Timorous]

This was in January 2022.

AMD demonstrates its next-gen Zen4 Ryzen 7000 CPU in Halo Infinite with all-core frequency of 5GHz - VideoCardz.com

Ryzen 7000 is hitting 5.0 GHz on all cores, claims AMD During its 2022 Product Premiere AMD demonstrated its next-gen processor with a short gameplay video. AMD not only confirmed the leaks featuring a unique AM5 CPU integrated heat spreader design but also confirmed it will be the first...

videocardz.com

Zen 4 launched in September 2022.

The Zen 5 GB6 leak was from November 2023.

Given AMD's history of leaks and teasers, I don't think there is very strong evidence to believe that the ES was running at clocks very far from final targets.

Even assuming the 3600 is a true figure there are a bunch of variables we just do not know so any comparison to other leaks / info is a bit premature. Any definitive claims of it is BS or it is gospel are just pointless right now, wait for reviews to make those statements.

All I know is that 40% would be out of the ordinary but is not outside of possibility given the scope of changes. 20% is far more expected given prior bumps but with the scope of changes it would be pretty lacklustre IMO.

 

[inf64]

Why are all of you assuming those GB numbers are correct? What is the source, RGT?