Right. Maybe it's higher than 10-15%, given the + (doubtful it's over 30%, however), but I find it unlikely that only Zen 5's IPC increase was measured in a different way from the rest.I tried to say this earlier but I got nowhere with it. It doesn't make sense to sandbag Zen 5 and change how it's measured without any note of it on the document. I can't see the logic for why they wouldn't keep the IPC measurement consistent.
Ok, look at this this way: does it makes sense that all those monumental changes to the core would result in 10-15% IPC jump versus Zen 4? Especially given how much IPC AMD has managed to get with much less transistor investment in previous iterations. It does not make any sense, right?I tried to say this earlier but I got nowhere with it. It doesn't make sense to sandbag Zen 5 and change how it's measured without any note of it on the document. I can't see the logic for why they wouldn't keep the IPC measurement consistent.
Didn't know there was any other notable forums similar to Anandtech.. I'll have to check those out.
Ok, look at this this way: does it makes sense that all those monumental changes to the core would result in 10-15% IPC jump versus Zen 4? Especially given how much IPC AMD has managed to get with much less transistor investment in previous iterations. It does not make any sense, right?
I think there's like a 90% chance it does better than what's shown in that slide. I can easily see a scenario where it gets over 20% IPC uplift.Ok, look at this this way: does it makes sense that all those monumental changes to the core would result in 10-15% IPC jump versus Zen 4? Especially given how much IPC AMD has managed to get with much less transistor investment in previous iterations. It does not make any sense, right?
...what does "IPC" stand for in this context, again? (Perhaps "IPC" is short for nT SPECint rate iso-clock performance. Or perhaps something else.) And which CPUs and computers (be they projected, simulated, or real) are being compared? (Obviously this depends on who the target audience was for this presumed/ alleged presentation and when it happened, if it happened.) Inconveniently, the corresponding slide with the all-important end notes which explain it all is MIA.I tried to say this earlier but I got nowhere with it. It doesn't make sense to sandbag Zen 5 and change how it's measured without any note of it on the document. I can't see the logic for why they wouldn't keep the IPC measurement consistent.The 19% from Zen 3 and 14% from Zen 4 is interesting. If they're listing those, then any scenarios where Zen 3 and 4 fell short (see: servers under load) aren't the bar here - the IPC they list and try to achieve is using the averaged upper bounds for these IPC figures which is relevant especially for client. It would be odd and.... convenient if for Zen 5, the number is some secret lower bound in a server scenario while they list their more general IPC figures in Zen 3, 4.
It's (new core SPECInt Rate nT/cores) / (old core SPECInt Rate nT/cores) at iso-clocks. i.e. Turin 128C is 46-52% faster than Genoa 96C (in this benchmark).Assuming for a second that these slides contain some bits of valid info in the first place...
...what does "IPC" stand for in this context, again? (Perhaps "IPC" is short for nT SPECint rate iso-clock performance. Or perhaps something else.) And which CPUs and computers (be they projected, simulated, or real) are being compared? (Obviously this depends on who the target audience was for this presumed/ alleged presentation and when it happened, if it happened.) Inconveniently, the corresponding slide with the all-important end notes which explain it all is MIA.
Obviously, consistency of the comparisons suffer if for example Zen 5c is a focus. It's suggesting itself to make comparisons of Zen 5c with Zen 4c. But that's where there is a discontinuity: There is no Zen 3c... As another example, the Zen 1 --> Zen 2 --> Zen 3 comparison chain already suffers from Zen 1 topping out with a 4-chiplet 32c processor, whereas both Zen 2 and Zen 3 have a 9-chiplet 64c processor at the top. (Ignoring the 17-chiplet processor at the very top of Zen 3 for a moment.) Or if you take desktop, you had a monolithic CPU in Zen 1 but MCMs both in Zen 2 and in Zen 3.) So, asking purely rhetorically, by which method and apparatus do you (or AMD, or MLID :-> ) isolate core architecture performance characteristics from computer performance characteristics? And do you (or AMD) even want to do so in the first place, for a given purpose?
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PS: Would be good if folks who use the TLA "IPC" submit enough context for everyone to get what they actually mean by it. Provided they have thought about this "IPC" thing as far, that is. Or just write out what they mean, instead of using "IPC" which means everything and nothing. Unless they want their post mean everything and nothing, then that's fine of course.
edit: punctuation
Ok, look at this this way: does it makes sense that all those monumental changes to the core would result in 10-15% IPC jump versus Zen 4? Especially given how much IPC AMD has managed to get with much less transistor investment in previous iterations. It does not make any sense, right?
That can't be true as he often has some great guests, unless you're also claiming that those same guests are just as dumb to appear with him.Everyone hates MLID, almost no one is carrying water for him. It's the most reluctant acknowledgement for the entire HW community if he's got something directionally accurate.
What's possibly telling about the recent Zen 5 IPC leak/rumor for those who saw (10-15% IPC increase) is that various big names have been real quiet since the announcement and, in other forums, they suspect it's an accurate and legitimate leak.
It's pretty funny if true, because even at 25% they'd technically still be short of Firestorm by a smidge on perf/GHz in some stuff, but similar enough - but now you'd be looking at a much more obvious failure to close a gap there with Firestorm or even an X4.
But it's also quite possible there's a detail missing e.g. it's for servers under some constraint.
Zen 5 DOOMED. that should get some clicks:Thanks for the reminder, I have been slacking off here. Here is a good discussion with Wendell:
If AMD were to offer such figures, would it be (new core SPECInt Rate nT/cores/clock) / (old core SPECInt Rate nT/cores/clock), i.e. new and old machines running at their "native" but different clocks? I.e. clock normalization happening in postdiction, not physically in the test runs?It's (new core SPECInt Rate nT/cores) / (old core SPECInt Rate nT/cores) at iso-clocks.
Further, if these were AMD's figures from physical samples (or simulations, but not mere projections), would something like "p…q+" refer to the fact that SPECint consists of different benchmarks (hence the …), and that all of the included benchmarks came out ≥p and most but not all of them were ≲q (hence the +)?i.e. Turin 128C is 46-52% faster than Genoa 96C (in this benchmark).
No not yet, but I wrote about a few possible outcomes in the past. Zen 5 is the most difficult one to "guess" as we have so much conflicting data floating around.I'm sure I missed it, but have you given your offical Zen 5 prediction yet?
Anemic SerDes bottlenecking the throughput?It's (new core SPECInt Rate nT/cores) / (old core SPECInt Rate nT/cores) at iso-clocks. i.e. Turin 128C is 46-52% faster than Genoa 96C (in this benchmark).
I know my prediction is that it will be fast and furious! 🚗🔥🔥🔥🚓🚓🚓 🚙🤣I'm sure I missed it, but have you given your offical Zen 5 prediction yet?
This makes more sense. Shorter time to market. And disabling HT would improve power efficiency and provide maximum 1T performance. Cinebench fans will be sad though.
Disabling HT doesn't move the performance or efficiency needles much at all. The reason SMT gets performance gains is by keeping the execution ports active when the main thread has to wait on accesses to main memory and can't execute anything or the instructions aren't using all of the available execution ports because the current mix skews heavily to one type of operation.
If MLID is half credible then he gave some hint that the improvement in Cinebench is quite big but is also an outlier that is not representative of the average IPC improvement wich is significantly less if we are to believe his words.
Yes it doesn't make sense.I tried to say this earlier but I got nowhere with it. It doesn't make sense to sandbag Zen 5 and change how it's measured without any note of it on the document. I can't see the logic for why they wouldn't keep the IPC measurement consistent.
Didn't know there was any other notable forums similar to Anandtech.. I'll have to check those out.
With a caveat that we don't know L2 and L3 capabilities.But I am just repeating the obvious. Your post is quite unambiguous about it.That sounds about right for a wider, generally beefier core but without improvements on the memory side past the L1 caches? Loads that are gentle on the memory system should see major improvement, things like games that push it hard should see much less.
Then I'd assume Zen6 to get very little improvement on cinebench, but potentially a lot in games if it manages to push down average latencies.
SMHIf Zen5 on AM5 will be limited to 16C with ~15% perf increase while bumping price it'll be a dud.
Unless we're getting a Zen5 core count increase to 24/32C (whether through 24/32C or 16P+8/16E), I think buying Zen4 at Black Friday at a discount will be a much better option.
He did not say anything remotely close to that for Zen 4.I have this annual architecture meeting where we go over everything that's going on, and at one of them (I won't say when) the team and I went through Zen 5. I learned a lot, because of nowadays as running the roadmap, I don't get as close to the design as I wish I could. Coming out of that meeting, I just wanted to close my eyes, go to sleep, and then wake up and buy this thing.