Has there been any news out of Microsoft's devices team since Panos Panay left?Surface is a meme.
Intel has said many things lately but many of them haven't become true, especially when they compare their processes to TSMC.Intel has said they will have a process lead over TSMC with 18A.
Nooooot quite.
MS skipped phones, realised the depth of their mistake too late, started an ambitious project to make a real MS Phone that was actually pretty great (everyone who had an early years MS phone told me of how it was wonderfully superior to Android), decided for some reason to drop their custom phone OS, I imagine they must've realised they were too late and would never get the large pool of 3rd party devs that Android did, and just copied Google for a few years before giving up for good.
So it's sort of a "skipped, tried late, failed, tried a weak copy, gave up for good". Or so I recall anyway.
Where is this coming from?View attachment 96643
"The MX6 data type in AIE-ML v2 offers up to 3X higher TOPS (trillions of operations per second)-per-watt than the AIE-ML compute tile architecture"
MX6 vs INT8.
Where is this coming from?
So... didn't skip phones.Nooooot quite.
MS skipped phones, realised the depth of their mistake too late, started an ambitious project to make a real MS Phone that was actually pretty great (everyone who had an early years MS phone told me of how it was wonderfully superior to Android), decided for some reason to drop their custom phone OS, I imagine they must've realised they were too late and would never get the large pool of 3rd party devs that Android did, and just copied Google for a few years before giving up for good.
So it's sort of a "skipped, tried late, failed, tried a weak copy, gave up for good". Or so I recall anyway.
So, after some napkin math - with 64 AIE-MLv2 tiles as per the AllTheWatts tweet, we end up at ~160 INT8 / MX6 TOPS.AMD Enables Single-Chip Intelligence for AI-Driven Embedded Systems with 2nd Gen Versal Devices
Editor’s Note: This content is contributed by Manuel Uhm, Director of Versal Adaptive SoC Marketing, AMD Adaptive SoCs and FPGAs. As embedded AI, video, and control applications explode, there is a growing need for heterogeneous processing to accelerate end-to-end compute within tight area...community.amd.com
Assumptions: 2 row, 8 column sub-arrays. Operating conditions: 1 GHz Fmax, 0.7V AIE operating voltage, 100°C junction temperature, typical process, 60% vector load, % activations = 0 < 10%. Actual performance will vary when final products are released in market. Performance projections as of March 2024. (VER-023)
What @adroc_thurston saying is that the AI push will be similar to the Touch Screen and Touch UX push of Windows 8. AKA: Another desperate push from MS to not lose another potential big stream of revenue.So wouldn't you think after almost two decades of touch screen computing on windows being a thing they'd stop making them? So charitable of the OEMs to sell touchscreen PCs at a loss for so long, very brave. lmao
It's a possibility AMD is already preparing for 2025 and/or 2026 MS requirements on the minimum amount of TOPs for Windows AI...So, after some napkin math - with 64 AIE-MLv2 tiles as per the AllTheWatts tweet, we end up at ~160 INT8 / MX6 TOPS.
Per chips and cheese, Hawk Point AIE runs at 1.6GHz. Strix could be 8 row, 8 columns. Its too good? Is MS actually going to use all this?
There is a lot of good info here about AIE-MLv1 - Ryzen AI column architecture and tiles — AMD Riallto 1.0 documentation
LMAO.What @adroc_thurston saying is that the AI push will be similar to the Touch Screen and Touch UX push of Windows 8. AKA: Another desperate push from MS to not lose another potential big stream of revenue.
Let's remember Windows 8? Where MS created a touch-centric UX with a Desktop UX bolted on. And treated K&M as second-place users by literally changing key combinations and others things to accommodate for Touch UX interactions, etc, etc, etc.
MS basically required Touch Screen for Premium Windows Laptops designs and was also pushing big for W8 Tablets, be it Arm or X86. Which is no different from their current push with bolting-on AI features on Windows, pushing Co-Pilot key on keyboards and requiring SoC manufacturers to include an big and expensive NPU that will be useless for 95% of the cases.
Whatever AMD put in Strix Point (probably Cadence Vision IP cores like they did for Van Gogh at Microsoft's request at the time) is something that got into the design some 3 years ago.I'm still in disbelief that we lost a SLC in Strix Point, which would greatly improve CPU performance (Specially due to Zen Mobile halved cache) and would provide a insane uplift for the GPU, making its performance even closer to a discrete GPU, but on thin and light devices with low power. Instead we get an useless NPU that will be power gated at 95% of the cases and is basically dead Si.
Am I missing something? Like Phoenix before it the Strix Point NPU is Xilinx AIE. Strix Point was always going to have an NPU because Phoenix did. But the story presented is that they adjusted the size of it more recently.Whatever AMD put in Strix Point (probably Cadence Vision IP cores like they did for Van Gogh at Microsoft's request at the time)
You're right. Van Gogh and Rembrandt use the Cadence Vision IP cores (CMVL blocks that we saw back in 2020 leaked roadmaps). Phoenix uses Xilinx IP as per AMD's published specs, and Strix Point probably follows suit.Am I missing something? Like Phoenix before it the Strix Point NPU is Xilinx AIE. Strix Point was always going to have an NPU because Phoenix did. But the story presented is that they adjusted the size of it more recently.
16MB IC(SLC) wouldn't be that big. <=10mm2Remember, Strix Point is already ~225mm². Imagine if it also had a SLC. Would be to big of a core to be commercially viable for AMD.
If anything, uzzi kind of indirectly said that Strix Halo will have that kind of unified cache. Point lost it, but Halo is a plain gaming oriented device.I'm still in disbelief that we lost a SLC in Strix Point, which would greatly improve CPU performance (Specially due to Zen Mobile halved cache) and would provide a insane uplift for the GPU, making its performance even closer to a discrete GPU
I find something weird about this argument that AMD had to cut the SLC, to fit in a bigger NPU due to die size constraints.Remember, Strix Point is already ~225mm². Imagine if it also had a SLC. Would be to big of a core to be commercially viable for AMD
I find something weird about this argument that AMD had to cut the SLC, to fit in a bigger NPU due to die size constraints.
Why?
Why couldn't AMD fit in both a big NPU and an SLC?
Erm. You think a low-midrange chip is going to take advanced packaging? That costs quite a bit you know? And is limited by how much substrate is available? (hint: not enough for everyone)It's not like they are breaking a reticle limit. In fact, the rumoured 225 mm² die size for Strix Point is already exceeding the 214 mm² limit that's needed for four dies per reticle.
When did I talk about chiplets or advanced packaging???Erm. You think a low-midrange chip is going to take advanced packaging? That costs quite a bit you know? And is limited by how much substrate is available? (hint: not enough for everyone)
🤔
moneyWhy couldn't AMD fit in both a big NPU and an SLC?
That's not how aspect ratios work dawg4 chips per reticle = 214 mm² × 4
Strix Point is replacement for Phoenix. Those APUs are always designed with AS LOW COST AS POSSIBLE to be used on desktop after x months of Mobile use.I find something weird about this argument that AMD had to cut the SLC, to fit in a bigger NPU due to die size constraints.
Why?
Why couldn't AMD fit in both a big NPU and an SLC?
It's not like they are breaking a reticle limit. In fact, the rumoured 225 mm² die size for Strix Point is already exceeding the 214 mm² limit that's needed for four dies per reticle.
1 reticle = 858 mm²
4 chips per reticle = 214 mm² × 4
Since they are already beyond the optimal die size to have 4 chips per reticle, and can have only 3 chips per reticle... why not just slap in an SLC too? A 16 MB would only add like 10 mm².
Max die size to have 3 chips per reticle is 286 mm².
nope.Strix Point is replacement for Phoenix
nope.Those APUs are always designed with AS LOW COST AS POSSIBLE to be used on desktop after x months of Mobile use.
Oooh. If Strix Point is not a direct succesor to Phoenix, then is it an entirely different class of APU?nope.
You can design the die such that it fits to the aspect ratioThat's not how aspect ratios work dawg
Yes it's more expensive.Oooh. If Strix Point is not a direct succesor to Phoenix, then is it an entirely different class of APU?
No you don't, all modern chips have pretty painful shoreline limitations to fit all the I/O.You can design the die such that it fits to the aspect ratio
Strix Point is a tier above Phoenix. It's meant to slot into Premium segments only.Oooh. If Strix Point is not a direct succesor to Phoenix, then is it an entirely different class of APU?