Recent content by Olikan

  1. Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

    humm... Zen4 L3 bandwidth is ~50% higher, userbenchmark sees a ~50% increase :smirk:
  2. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    At this point, i doubt the extra cost is more than $15, this is an old tech for AMD... they could easily made each chiplet larger, say 128-bit bus, the complexity would be halved, and would still had a good flexibility If anything, the tiny size of the chiplet means the savings of a yield...
  3. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    another interesting thing about these MCDs, is that AMD may reuse them for FGPAs
  4. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    What are the odds of something crazy like LPDDR5x? RDNA2 was surprising with its small bus. RDNA3 is rumored to have even bigger IF, more compression and clocks over 3GHz.... bandwidth shoundt be a problem, but latency might... a cheap, low latency and power efficient memory, might be good...
  5. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    Keep in mind, from the other patents: dual vector and super simd, both relie on auxiliar caches near the registry files
  6. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    Indeed, just the patent have weird ways to explain it... "a CU surrounded by L0s"
  7. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    UNIFORM CACHE SYSTEM FOR FAST DATA ACCESS https://www.freepatentsonline.com/y2022/0188232.html Someone at twitter found this patent some time ago, only now looking again at @Kepler_L2 diagram of RDNA3, i think i understood... Each SIMD will have it's own L0 cache, if a miss, it will look at...
  8. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    Pure expeculation: for next generation, AMD might improve the "dual vector issue" to be more flexible... Like 4 lanes of SIMD16, for a "quad vector issue"...do 1 wave 64, 2 wave32 and 4 wave16 per clock... Maybe even do unussual issues like wave48 + wave16
  9. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    It's a follow up of the patent "super-simd", RDNA3 can (aparently) chain mutiple instructions in theyr dual ALUs, pretty much bouncing the results of one alu to another... it's nothing alike the old gpus This last patent descibes that a compiler keeps track of any dependencys, and if it finds...
  10. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    Vliw compiler is back... but more advanced https://www.freepatentsonline.com/y2022/0188120.html
  11. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    I really can't remember another gpu that can do a wave64 in a single clock, very impressive.
  12. Question AMD Phoenix/Zen 4 APU Speculation and Discussion

    not a pro at this, but will do my best It alleviates one of the most important GPUs bottleneck: register file... (a major bottlenck of GCN gpus) doing a wave64 in 2 clocks means twice the time it needs to hold data... Problem shows up when the gpu needs to execute a critical wavefront, but the...
  13. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    Whats your theory on the double wavefront? Just saw at twitter an interesting speculation: the gpu launches 2 wave32 at the same time, emulating as 1 wave64... this would allow the gpu to launch 1 wave64 per clock
  14. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    Nope, a wavefront will use as many shaders it can... I can see 2 uses of it: 1- Similar to hypertreading in CPUs, a way to use all resources avaible when possible. The drivers would need to be aware of it, will have diminushing returns If devs fine tune for it; 2- to Double the shaders...
  15. Discussion RDNA 2 6nm Refresh

    There was any talk about EUV improving Fmax?
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