Yes, but that does not detract from the fact that chiplets offer greater versatility within those discrete SKU groups than just one whacking huge core/cache die with bad yields determining core count binning.
You still get the option of die binning with chiplets, but on top of chiplet scaling...
Well yes and no.
Yes in theory, but no in the case of ARM where the synthesizable IP probably has the greater part of the IP interoperability prebaked in as long as you are using just their IP, combined with the fact that ARM works with TSMC and Samsung to synergize on process.
(the uncore...
Hmmm, seems the exact shape of the forksheet move is still in question:
https://www.imec-int.com/en/articles/outer-wall-forksheet-bridge-nanosheet-and-cfet-device-architectures-logic-technology
Also design costs.
Designing beeeg dies has beeeg costs to go with it - AI/ML design tools may be helping to take some of that load off as it gets more and more complex, but it's still anything but trivial to design a 600mm² die vs a 100-150mm² one.
Chiplets allow for a very versatile...
Saw this imec roadmap in a video from Ian Cutrress and noticed something nu in the back-side interconnect thing I'd never seen before:
"Local signal lines"
Wonder if this is moving from purely power delivery to IO/data as well?
Edit: It's not labeled as such, but I think the different icon...
If you thought ReSTIR was a game changer then wait till you see this thing in action....
https://www.lalber.org/2025/04/markov-chain-path-guiding/
Real time path guiding with single scattering in volumes 😎
If Switch 1/2 and the post Gamecube consoles show us nothing it's that HW spec isn't really all that it's cracked up to be when it comes to selling consoles.
It's the platform UX (controllers + UI + fan noise etc), game library and the brand that determines its ultimate success.
Medusa/Strix...
PCIe 6.0 on AMD (Venice by the sound of it):
https://www.techpowerup.com/338125/keysight-enables-amd-to-showcase-electrical-pci-express-compliance-up-to-64-gt-s
Update on HIP RT/RDNA4 performance, I scoured the GitHub repo and found this:
https://github.com/GPUOpen-LibrariesAndSDKs/HIPRT/issues/35#issuecomment-2814200540
Evidently they are likely updating it to the nu HIP 7, with optimisations likely to be included along the way.
For what reason?
Does Steam Deck not sell well enough to justify the VG production and AMD/TSMC are bitter about this?
Or is Valve delinquent on paying chip royalties?
Oh ye RDNA5/UDNA/woteva dGPUs will likely launch pretty close to at least one console.
Be interesting to see where Valve lands in terms of what semi custom stuff they have next on their roadmap with AMD.
Actually that's pretty par for the course.
The first PC APU with RDNA2 (Rembrandt IIRC) was announced in Jan 2022, over a year after PS5 and XSX/XSS launched in 2020.
Then Steam Deck with Van Gogh/Aerith was announced just a month later in Feb 2022.
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