I think availability will be fine for Medusa Halo specifically. The volumes will not be there to support mainstream Zen6 products, but a relatively low-volume halo product that's also expected to release fairly late in the cycle, I think there would be enough memory for them.
There would be a...
I dunno. This document can't tell you, because it only defines how APX and AMX registers should be handled, if present. AMD64 just the proper name for the ISA that's often called x86-64, it doesn't imply AMD is involved.
The terminology is still confusing you. These are just the architectural registers for APX and AMX.
They being called "temporary" means that after a function call, the function that was called can freely use them to store values without first preserving what already exists in them, and likewise...
... Do you think they only start the production of the regular chips after a month of twiddling their thumbs?
None of the timelines have any slack in them. If they could do what you claim, they would also start the production of the regular chips a month earlier for getting to market one month...
Note that starting with Zen5, the TSVs don't go on the CCD. The CCD is face down on top of the cache chiplet, so no holes need to be drilled through its substrate. They just need to add vias and pads through the metal layers for the interconnect, and these don't need extra manufacturing steps...
No. Because AMD cannot spend more money today to have more chiplets with 3D cache. The lead time for increasing capacity is measured in years, plural. For all intents and purposes, for the entire Zen 5 generation they have a fixed amount of chiplets with the added cache, they already know how...
The integration capacity is still limited. AMD keeps buying more capacity every generation, but it's slow to build. They cannot put vCache on every chip next year by just spending some money.
There is no engineering effort to gut the FPU, AMD has already designed it to be configurable. You just pick whether you want 256-bit or 512-bit ALUs, and I don't see a world where the die area would be better spent on doubling the SIMD execution width, and not in the GPU.
And again, 256-bit...
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