Discussion Apple Silicon SoC thread

[Eug]

M1
5 nm
Unified memory architecture - LP-DDR4
16 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 12 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache
(Apple claims the 4 high-effiency cores alone perform like a dual-core Intel MacBook Air)

8-core iGPU (but there is a 7-core variant, likely with one inactive core)
128 execution units
Up to 24576 concurrent threads
2.6 Teraflops
82 Gigatexels/s
41 gigapixels/s

16-core neural engine
Secure Enclave
USB 4

Products:
$999 ($899 edu) 13" MacBook Air (fanless) - 18 hour video playback battery life
$699 Mac mini (with fan)
$1299 ($1199 edu) 13" MacBook Pro (with fan) - 20 hour video playback battery life

Memory options 8 GB and 16 GB. No 32 GB option (unless you go Intel).

It should be noted that the M1 chip in these three Macs is the same (aside from GPU core number). Basically, Apple is taking the same approach which these chips as they do the iPhones and iPads. Just one SKU (excluding the X variants), which is the same across all iDevices (aside from maybe slight clock speed differences occasionally).

EDIT:



M1 Pro 8-core CPU (6+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 16-core GPU
M1 Max 10-core CPU (8+2), 24-core GPU
M1 Max 10-core CPU (8+2), 32-core GPU

M1 Pro and M1 Max discussion here:

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M1 Ultra discussion here:

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M2 discussion here:

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Second Generation 5 nm
Unified memory architecture - LPDDR5, up to 24 GB and 100 GB/s
20 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 16 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache

10-core iGPU (but there is an 8-core variant)
3.6 Teraflops

16-core neural engine
Secure Enclave
USB 4

Hardware acceleration for 8K h.264, h.264, ProRes

M3 Family discussion here:

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M4 Family discussion here:

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[Glo.]

This was why I always had a hard time seeing Apple doing the ARM transition for Macs. Macs have MUCH less volume than iPhones, and they needed more chips to cover the range of Macs. It seemed like chip economics were really against them to doing ARM Macs. But they did do it...

Mac are important part of Apple PLATFORM. Do not consider this product as a separate part of it, and define it by typical PC standards.

Apple has a PLATFORM. And think about it in those terms. Not separate units, devices, like on PC market.

 

[repoman27]

They've been doing three separate designs since M1.

M3 Pro got gutted.

TSM has been good at ramping nodes into volume since N7.
Not really an achievement?

Lol. As usual, you're confidently wrong about everything, because you fundamentally lack knowledge of the space. I've seen your post history so I'm not even going to bother to engage.

Which part of the M3 is a trainwreck meme again? The part where Apple hard launched products containing a family of three SoCs manufactured using first generation N3 just 10 months after the process reached volume production and right on time for the most important sales quarter of the year?

How does that compare to Intel completely missing 2023 including the holiday quarter with MTL, which is mostly fabbed by TSMC and mostly on legacy nodes anyway? How does it compare to Qualcomm paper launching the TSMC N4 Snapdragon X Elite more than 6 months out from release?

Don't get me wrong, I'm all for competition and what that brings, but Apple and TSMC just threw down a gauntlet here and Intel and Qualcomm need to start executing.

 

[Tigerick]

Lol. As usual, you're confidently wrong about everything, because you fundamentally lack knowledge of the space. I've seen your post history so I'm not even going to bother to engage.

Which part of the M3 is a trainwreck meme again? The part where Apple hard launched products containing a family of three SoCs manufactured using first generation N3 just 10 months after the process reached volume production and right on time for the most important sales quarter of the year?

How does that compare to Intel completely missing 2023 including the holiday quarter with MTL, which is mostly fabbed by TSMC and mostly on legacy nodes anyway? How does it compare to Qualcomm paper launching the TSMC N4 Snapdragon X Elite more than 6 months out from release?

Don't get me wrong, I'm all for competition and what that brings, but Apple and TSMC just threw down a gauntlet here and Intel and Qualcomm need to start executing.

Yeah, seems like AMD's Strix Point has been delayed by one quarter and we won't be seeing Sarlak until 2025.

OTOH, we might be seeing M4 series by end of next year/early 2025. At this stage, I think Apple will stick to N3B process for M4 series. If anyone still have doubt about yield issues, it is just early issue with new process. Think how many transistors M3 Max is having?

 

[Anhiel]

This was an interesting launch.

The A17 Pro and M3 diverge on features. (?) A17 has a beefier neural engine 2x as big, while M3 got the dynamic caching on the GPU which from what I understand A17 Pro does not have or does not have enabled.

Then we have M3 Pro which is 1,5x M3 not 2x M3. It seems there is effort to make it cheaper entry level for the Pro than the previous gen.

Then we have binned memory buses in addition to CPU and GPU. Aggain M3 Max seems huge with 5/6 the transistors of an M1 Ultra. No wonder the bins have to be more aggresive on a new process

We have very little comparison to M2 generation, focusing instead on comparing to M1.

From the graphs we saw, the power consumtion is slighthly higher M1 vs M3 on CPU but that was the case for M2 as well. We have no info on efficiency improvements compared to M2. We have no battery life improvement compared to M2 gen.

Would like to see the GPU curves compared, how much more power the max Max die consumes - a guess is 5x12 + 4x0,5 = 65-70 W for the CPU and 50 W for the GPU. How well can the 14" cope with a full blown Max at max load ?

Is there anything useful on those die shots to be seen ? The memory bus (?) on the sides of the M3 Max seems particullary blown up compared to other chips.

Is there any way to compare the costs of configurations gen on gen ? I got completely lost and confused on configurations site this time.

Is the M4 generation coming like this next year ?

The Anandtech article said 17W for the GPU part. So 4 x 17 = 68 W for the MAX.
Welp, last year or so (don't remember) I did post a projection based on the node change that would give at best 18% clock speed and that it would give 20.21 TOPS for 16 NE configuration. Now, that we know it's only 18 TOPS back calculated gives ~16% clock. For the 10 to 12 core GPU I had it at 15W (Pro 20W; MAX 53W).
So it looks like all is due to clockspeed increase while being slightly less efficient but still reasonable. It seems IPC gains are with the efficiency cores only. The overall sizing (or cut down) is most likely done to keep overall consumption similar. They hit the target for generational "improvement" even if design wise it's not exciting.

 

[Eug]

Guess most people are using their MBP for basic tasks, for a lot more money than something like a $500 laptop with 8GB/256GB. Apple is lucky to have such users. I'm guessing at best, MacOS leaves 6 GB RAM available for application usage?

They designed the M3 for the lowest common denominator, not the MBP. I don’t know if there is a significant technical consideration or if it’s strictly a marketing decision, but M3 is an 8 / 16 / 24 GB setup, for the iMac, MacBook Air, and the Mac mini. (Can M3 only support two memory chips?) The entry level M3 MacBook Pro gets the same treatment just because. I suppose they could have started it at 16 GB but then they would have needed to increase the base price, which wouldn’t look so good.

But yeah, most people getting these entry level “Pro” machines don’t actually need higher SoC performance and probably benefit a lot more from the long battery life. And fortunately, going from 8 to 16 GB on the M3 MBP still means a machine that’s cheaper than the M3 Pro MBP.

As for effectiveness of 8 GB, I can say that my wife and kid with 2017 MacBook Air 8 GB and 2015 13” MacBook Pro 8 GB are both perfectly happy with their machines. They are both running Monterey but that OS is still getting updates. Last update was last week.

And finally the Mx non-Pro MacBook Pro has a real reason to exist. Even though the memory only starts at 8 GB, the rest of the machine is fantastic. The old 13” Touchbar MBP was kept around for far too long.

 

[Heartbreaker]

(Can M3 only support two memory chips?)

I don't think I've ever seen LPDDR running multiple packages on a single channel. LPDDR runs at lower power and higher speed than desktop DDR, so may have tolerances that prevent multiple packages/channel.

 

[SarahKerrigan]

Mac are important part of Apple PLATFORM. Do not consider this product as a separate part of it, and define it by typical PC standards.

Apple has a PLATFORM. And think about it in those terms. Not separate units, devices, like on PC market.

Weren't you the person who was loudly and confidently insisting that Apple's cores were way too slow to ever do a platform transition? Just checking.

 

[Eug]

The M3 MacBook Pro also only gets 2 Thunderbolt ports. That makes sense with M3. The good news is that it has MagSafe now.

 

[repoman27]

I don't think I've ever seen LPDDR running multiple packages on a single channel. LPDDR runs at lower power and higher speed than desktop DDR, so may have tolerances that prevent multiple packages/channel.

Doing multiple packages per channel may be out, but you can configure the dies within a package in many different ways. You can do dual-rank with LPDDR, and/or run the devices in byte-mode to put two on a single channel. So up to 4 dies per 16-bit channel.

Apple is limited by their packaging here. With only 2 quad-die LPDDR packages per SoC package, they can only address 8 dies. They could do a differently packaged M3 with a larger substrate and use x64 octal-die LPDDR packages, with the dies internally configured as dual-rank. Or do a 32GB version using 32 Gbit dies.

As long as 8 Gbit dies are a thing and there's still a meaningful price difference between them and the next higher density, Apple will continue to sell M3 Macs with 8GB of DRAM. And it's still fine for iPads. It's the prices that Apple charges for additional DRAM and NAND that I'd like to see change.

 

[repoman27]

Think how many transistors M3 Max is having?

92 billion.

 

[trivik12]

I dont think there is anything in the new release that makes it a strong buy. $1600 for 8GB system is only for Apple faithful and a very narrow use case that is not met by M2 Air. More expensive laptops will cost more for M3 version. I expect corporate buys to drive this version rather than consumers buying 2K+ laptops except the core faithful. Rest in this recessionary environment.

Apple's Q3 will suck overall but services growth is more important. They have increased prices on some services and may be that will help for Q4

 

[FlameTail]

Question: What is the function of the EMX unit in Apple CPUs?

 

[igor_kavinski]

Hate that Apple thinks the base M3 MBP16 is useless with 128GB RAM. Regardless of technical reasons (which would be profit motivated anyway), it just superficially looks they want people to pay through the nose for the privilege of 128GB, even though the actual cost to upgrade looks reasonable (a bit over $1000). Would have helped people wanting 128GB at a lower price point. But of course, Apple expects their users to riddle themselves with debt.

 

[Eug]

Hate that Apple thinks the base M3 MBP16 is useless with 128GB RAM. Regardless of technical reasons (which would be profit motivated anyway), it just superficially looks they want people to pay through the nose for the privilege of 128GB, even though the actual cost to upgrade looks reasonable (a bit over $1000). Would have helped people wanting 128GB at a lower price point. But of course, Apple expects their users to riddle themselves with debt.

There is no M3 MBP16. MBP16 starts with M3 Pro. Also:

M3 - 2 chips
M3 Pro - 3 chips
M3 Max - 4 chips

 

[Doug S]

Yeah why do they only bin CPU and GPU.

Don't the NPU, caches and RAM controllers get defects?

The NPU is small, and disabling part of the cache is not easy - and even then it has to be deliberately designed for that. I think Apple is mostly doing market segmentation. Sure, there are some chips with a bad CPU or GPU core, or bad LPDDR5 controller. But under typical TSMC yields there aren't going to be nearly enough for the way Apple is segmenting e.g. the Macbook Pro pricing. If they want to have multiple configurations, most of the lower end ones will have all cores working just disabled.

Intel has been doing the same thing for ages - that's why overclocking mainstream stuff worked so well that Intel had to shut down it down and force people to buy the high end SKU if they wanted high end performance.

 

[Doug S]

https://x.com/t3mporarybl1p/status/1719317658255110416?s=20

Bizarre NPU stuff

There are die photos of both, if you compare them and measure the NPU area you can figure out if it is really twice as large or they are just counting differently. i.e. maybe the iPhone NPU supports INT8 and the Apple Silicon NPU only supports INT16. Qualcomm touted some big numbers for their NPU but it supports INT4 so it will have double the "performance" of one that supports INT8 but not INT4 and 4x the performance of one that supports INT16.

 

[Doug S]

OTOH, we might be seeing M4 series by end of next year/early 2025. At this stage, I think Apple will stick to N3B process for M4 series. If anyone still have doubt about yield issues, it is just early issue with new process. Think how many transistors M3 Max is having?

Why in the world would they use N3B for M4, when N3E will be available which performs better, uses less power, and is cheaper? OK not by much on any of those three metrics but something is better than nothing. But mostly because A18 will use N3E and M4 cores will be based on A18.

By pushing out the M3, M3P and M3M all at once a month or two after the iPhone I think that shows Apple has finally got their cadence sorted out and we'll start seeing new Apple Silicon every fall shortly after the iPhone launch. I've always said the 18 month thing was just happenstance the way the timing of the first couple iterations worked out. The smooth M3 launch (despite all the chaos around N3B) tells me they seem to have the kinks ironed out of that process.

 

[FlameTail]

The NPU is small, and disabling part of the cache is not easy - and even then it has to be deliberately designed for that. I think Apple is mostly doing market segmentation. Sure, there are some chips with a bad CPU or GPU core, or bad LPDDR5 controller. But under typical TSMC yields there aren't going to be nearly enough for the way Apple is segmenting e.g. the Macbook Pro pricing. If they want to have multiple configurations, most of the lower end ones will have all cores working just disabled.

Intel has been doing the same thing for ages - that's why overclocking mainstream stuff worked so well that Intel had to shut down it down and force people to buy the high end SKU if they wanted high end performance.

Yeah this is something I have wondered about Ryzen and Intel and now Apple.

So not every cut down version of a chip was cut down because it was defective?

Which then leads to a dilemma- why not simply make a smaller chip and big chip, instead of making big chips and disabling a ton of stuff to make low tier versions.

 

[FlameTail]

Why in the world would they use N3B for M4, when N3E will be available which performs better, uses less power, and is cheaper? OK not by much on any of those three metrics but something is better than nothing. But mostly because A18 will use N3E and M4 cores will be based on A18.

Yeah. It's bizarre to expect the succesor to use the same node. Especially when the chip designer in question is Apple and the fab TSMC will have a better node ready.

By pushing out the M3, M3P and M3M all at once a month or two after the iPhone I think that shows Apple has finally got their cadence sorted out and we'll start seeing new Apple Silicon every fall shortly after the iPhone launch. I've always said the 18 month thing was just happenstance the way the timing of the first couple iterations worked out. The smooth M3 launch (despite all the chaos around N3B) tells me they seem to have the kinks ironed out of that process.

So you are expecting new M chips ever year? Well, Apple is certainly rich but designing chips like this is certainly quite expensive and it's questionable if it will be worth it considering that the pace of the computer industry is slower than that of the smartphone.

 

[FlameTail]

Question: What is the function of the EMX unit in Apple CPUs?

*AMX

 

[FlameTail]

die shot analysis

 

[Tigerick]

Why in the world would they use N3B for M4, when N3E will be available which performs better, uses less power, and is cheaper? OK not by much on any of those three metrics but something is better than nothing. But mostly because A18 will use N3E and M4 cores will be based on A18.

By pushing out the M3, M3P and M3M all at once a month or two after the iPhone I think that shows Apple has finally got their cadence sorted out and we'll start seeing new Apple Silicon every fall shortly after the iPhone launch. I've always said the 18 month thing was just happenstance the way the timing of the first couple iterations worked out. The smooth M3 launch (despite all the chaos around N3B) tells me they seem to have the kinks ironed out of that process.

Geez, guess someone never learnt why Apple managed to release M3 series with N3B process when I have been saying for a while now. It is clear that TSMC's N3B process is progress fine with Apple launching A17 Pro and M3 series. Apple managed to release M3 series under a year of HVM of TSMC shows N3B is meeting Apple's requirements, do you agree?

If N3B is progressing fine, then why do Apple change process on upcoming A18 series but not M4 series as I suspected? Let's go back to difference N3B and N3E:



N3E shows better power efficiency or higher performance but not both. This is basic 101 of TSMC's claim. The difference is about 2-7% for power and 3-8% for performance. Pretty small difference I would say.

SRAM Cell Size: N3E has slight advantage but the difference is about 5%

However, the logic density is showing about 10% better reduction with N3B process: 1.6x vs 1.7x. Clearly Apple has been taking advantage of it with M3 Max: Compare to M1 Max with first gen of N5 process, M3 Max's transistor count has increased 61%. We don't know how big the die size of M3 Max is, but based on improvement of transistors count, clearly Apple is taking advantage of N3B process.

OTOH, iPhone's SoC does not need to scale heavily on transistor counts, A17 Pro only shows less than 20% increment of transistor count compared to A16. Thus, it is OK to switch upcoming A18 series to N3E process and taking advantage of better power efficiency (2-7%). Another reason of course is cost; iPhone is selling from $800 and up and I suspect A18 would be used for upcoming iPhone SE that is selling for around $500. By switch process, SoC's cost would be lower, thus justifying the move.

M4 series are difference story, if Apple is sticking to similar die size of M3 Max, M4 Max won't increase much in transistor count but at least we should be expecting around 100 billion of transistors. I am sure Apple will try to hit the 100 billion marks for marketing's sake. That's why I think Apple will stick to N3B process, cause N3E is not able to scale heavily on logic density. If based on TSMC's data, M4 Max with N3E process would hit 91.2 billion which Apple has achieved with M3 Max. Apple normally use the same process to prolong the investment, and if N3B process's yield is good and provides better logic density, why switching? Unlike iPhone, M3 Max notebooks are selling from $3,199 and above. Apple has the margin to continue using same process without redesign M4 series.

Technically, the reason N3B able to hit such a huge transistor is because they are using 25 EUV layers with double patterning. N3E is using lesser EUV layers without double patterning, these two process's design rules are different. Therefore Apple won't change process if there is real advantage of it, A18 series fit in the bills but not for M4 series. Do you think Apple will spend another millions just to change the design of M4 Max and make it smaller??? It does not make sense on M4 series, thus I am expecting M4 series continuous using N3B process.

It is OK to have wrong prediction, I have been wrong before, that's how we learned. This thread is way too long, I will let you decide which to believe...

 

[FlameTail]

My counterpoint would be that sooner or later, Apple will have to switch to a 3nm node with different design rule.

N3E and N3P have same design rule, dofferemt from N3B. I am sure Apple would like to use that sweet P-node that is N3P. For M5 perhaps? If as Doug says, they do an yearly release:

M3 = N3B = 2023 Q4
M4 = N3E = 2024 Q4
M5 = N3P = 2025 Q4

Considering TSMC N2 won't be out before 2026.

If it's not an yearly cadence, but the 18-month one:

M3 = N3B = 2023 Q4
M4 = ??? = 2025 Q2

What node will M4 use then? N3P should be available by that time so I bet that's what will be used.

 

[Doug S]

So you are expecting new M chips ever year? Well, Apple is certainly rich but designing chips like this is certainly quite expensive and it's questionable if it will be worth it considering that the pace of the computer industry is slower than that of the smartphone.

How many new CPU dies does Intel introduce per year? Sure the x86 market is larger, but they have to share it with AMD now. Apple has the advantage of only selling to the high end of the market, and the design cost for their cores is basically $0 since the iPhone pays for them. Sure there is plenty of NRE for the layout, mask set, stuff unique to Apple Silicon like the multi die connectivity but they save a lot getting the cores "for free".

So I don't think it would be that remarkable for Apple to go to a yearly cadence. If they don't I would expect a two year cadence. 18 months doesn't make a whole lot of sense, that was never the long term plan it just worked out that way.

 

[repoman27]

My counterpoint would be that sooner or later, Apple will have to switch to a 3nm node with different design rule.

N3E and N3P have same design rule, dofferemt from N3B. I am sure Apple would like to use that sweet P-node that is N3P. For M5 perhaps? If as Doug says, they do an yearly release:

M3 = N3B = 2023
M4 = N3E = 2024
M5 = N3P = 2025

Considering TSMC N2 won't be out before 2026.

If it's not an yearly cadence, but the 18-month one:

M3 = N3B = 2023 Q4
M4 = ??? = 2025 Q2

What node will M4 use then? N3P should be available by that time so I bet that's what will be used.

Don't forget about N3S, which should be available in time for Apple's 2024 chips.