Is the 4 MiB L2 for the Gracemont cluster confirmed? If true, extrapolating from Willow Cove L2 just the L2 cache would take ~5.8 mm2 per cluster which is about the same as a Willow Cove core + L2 (6.11 mm2). Makes me a lot more sceptical about the rumors of a single cluster being about as large as a single Golden Cove core unless the Golden Cove core grew a lot in area.
Alderlake 8+8 is over 50% bigger die than Tigerlake-H.
Won't be that big as the 8+8 die doesn't have the Thunderbolt or the IPU.
As there is already Alderlake pictures around wasn't that 8+8 die estimated to be around 310mm2?
It is definitely much smaller than thatAs there is already Alderlake pictures around wasn't that 8+8 die estimated to be around 310mm2?
It is definitely much smaller than that
It is definitely much smaller than that
Sounds like a lot until you realize 4 Willow Cores + Cache & Ring made up for less than 40% of total die area."Double" the core count plus much bigger cores.
So P-core offers over 50% more performance over E-core.Slides are up before their Hot Chips presentation, but if there's anything indicative of this is that they got the hybrid architecture working right now
Exactly. Their plan is to have 8 high-power cores that accomplish UI tasks, single threaded tasks, and poorly multi-threaded tasks as fast as Intel can possibly do them. Then keep on piling on more of the efficient cores to get better and better at the multi-threaded tasks.I'm starting to "get" the rationale behind ADL I think. 8 big, fast cores to compete with Zen 3 head-to-head against the 5800X. I know this is dangerous water I'm treading into but I think Intel is reasoning that *most* people don't really need more than 8 cores AND there is still a lot of software that doesn't scale in a linear fashion past 8 cores.
So adding the Gracemont cores solves quite a few "competition" problems:
What’s New: The U.S. Department of Defense, through the NSTXL consortium-based S2MARTS OTA, has awarded Intel an agreement to provide commercial foundry services in the first phase of its multi-phase Rapid Assured Microelectronics Prototypes - Commercial (RAMP-C) program. The RAMP-C program was created to facilitate the use of a U.S.-based commercial semiconductor foundry ecosystem to fabricate the assured leading-edge custom and integrated circuits and commercial products required for critical Department of Defense systems. Intel Foundry Services, Intel’s dedicated foundry business launched this year, will lead the work.
“One of the most profound lessons of the past year is the strategic importance of semiconductors, and the value to the United States of having a strong domestic semiconductor industry. Intel is the sole American company both designing and manufacturing logic semiconductors at the leading edge of technology. When we launched Intel Foundry Services earlier this year, we were excited to have the opportunity to make our capabilities available to a wider range of partners, including in the U.S. government, and it is great to see that potential being fulfilled through programs like RAMP-C.”
–Pat Gelsinger, Intel CEO
How It Works: Intel Foundry Services will partner with industry leaders, including IBM, Cadence, Synopsys and others, to support the U.S. government’s needs for designing and manufacturing assured integrated circuits by establishing and demonstrating a semiconductor IP ecosystem to develop and fabricate test chips on Intel 18A, Intel’s most advanced process technology.
“The RAMP-C program will enable both commercial foundry customers and the Department of Defense to take advantage of Intel’s significant investments in leading-edge process technologies,” said Randhir Thakur, Intel Foundry Services president. “Along with our customers and ecosystem partners, including IBM, Cadence, Synopsys and others, we will help bolster the domestic semiconductor supply chain and ensure the United States maintains leadership in both R&D and advanced manufacturing. We look forward to a long-term collaboration with the U.S. government as we deliver RAMP-C program milestones.”
Intel recently announced plans to become a major provider of U.S.-based capacity for foundry customers, including an investment of approximately $20 billion to build two new factories in Arizona. These fabs will provide committed capacity for foundry customers and support expanding requirements for Intel products.
Why It’s Important: The U.S. Department of Defense (DOD) has recently sought to diversify its approach to securing advanced microprocessors by leveraging commercially available technologies developed by U.S. companies. Other than Intel, the majority of U.S.-based chip designers are fabless, which means they design and sell integrated circuits that are fabricated by contract manufacturers called foundries. Today, more than 80 percent of leading-edge manufacturing capacity is concentrated in Asia1, leaving the DOD with limited onshore access to foundry technology capable of meeting the country’s long-term needs for secure microelectronics. The RAMP-C program was created to facilitate the use of a commercially viable onshore foundry ecosystem that will ensure DOD access to leading-edge technology, while allowing the defense industrial base to leverage the benefits of high-volume semiconductor manufacturing and design infrastructure of commercial partners like Intel.
Sapphire Rapids XCC 15C tile is exactly 426.4 mm².Intel Sapphire Rapids-SP Xeon CPUs To Feature 4 8-Hi HBM2E Stacks, 14 EMIB Interconnects, Full XCC Die Measures Around 400mm2
Intel has further detailed the die and package sizes of its Sapphire Rapids-SP Xeon CPUs with HBM memory & Ponte Vecchio GPU.wccftech.com
WCCF has some of the slides pertaining to Sapphire Rapids... tile is ~400 mm2 and the HBM2 model has (up to?) 64 GB possible.
I don't think we have any indication of die sizes for Alder Lake yet.
So P-core offers over 50% more performance over E-core.
Now Tiger Lake U -> Alder Lake P... that's going to be a lot bigger. "Double" the core count plus much bigger cores.
Sapphire Rapids XCC 15C tile is exactly 426.4 mm².
Tiger Lake 4+2 LP die is 13.6 mm x 10.7 mm = 145.5 mm².
Tiger Lake 8+1 HP die is 18.9 mm x 10.5 mm = 198.5 mm².
I don't think we have any indication of die sizes for Alder Lake yet.
I believe > = Greater Than. Or?
OK, we do know the package dimensions, so I went ahead and measured these renders from the Architecture Day presentation (which are probably not all that accurate, mind you).We have rendered picture and backside picture from Intel, from where die dimensions are about 12mm x 26mm.
And we got this:
View attachment 49188
Even DDR5-phy in Alderlake desktop is huge, as is PCIE phy. And as XE-gpu is basically same as it is in Tigerlake anyone could calculate actual die sizes with even more accuracy if wanted.
Need to be careful here. >50% at high power levels. When running at low power levels, there isn't much gain.According to the hot chips presentation: 50%:
OK, we do know the package dimensions, so I went ahead and measured these renders from the Architecture Day presentation (which are probably not all that accurate, mind you).
View attachment 49198View attachment 49200View attachment 49201
Which gives us the following:
ADL 2+8+2 LP: 18.4 mm x 11.2 mm = 206 mm².
(For reference, CML 10+2 HP is 22.4 mm x 9.2 mm = 206 mm².)
ADL 8+8+1 HP: 25.2 mm x 12.6 mm = 318 mm².
(For reference, RKL 8+1 HP is 24.0 mm x 11.5 mm = 276 mm².)
And wait for it... ADL 6+8+2 LP: 29.8 mm x 14.6 mm = 435 mm².
(For reference, SPR 15C tile is 20.8 mm x 20.5 mm = 426 mm².)
There is no way Intel can maintain anything like their traditional margins with 10nm client dies that size.