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N
naukkis
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N
naukkis
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
Uop cache is about that energy efficiency difference between decoding instruction and fetching it from mop cache. MOP cache will take...
Today at 7:49 AM
N
naukkis
replied to the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
.
Didn't AMD tell that 512-bit FPU is optional in Zen5 designs? Using 512bit FPU pipelines and load/store engine and trying to optimize...
Today at 3:39 AM
N
naukkis
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
Problem is that Intel did extract everything they could from chip - and gone too far. They become unstable. Big part of that is that SMT...
Sunday at 1:27 PM
N
naukkis
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
Point that should be seen is that in Intel hybrid cpu designs HT gain in best case scenario isn't 30% but at best 10%. It should be...
Sunday at 2:05 AM
N
naukkis
replied to the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
.
No, what they did do with Zen3 is to use marco-ops instead of micro-ops - they reduced PRF usage by letting macro-ops transfer data...
Apr 22, 2024
N
naukkis
reacted to
Timorous's post
in the thread
Discussion
Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)
with
Like
.
The correct numbers are clearly the measured ones from the review in question. It may not make much difference or change the conclusion...
Apr 20, 2024
N
naukkis
replied to the thread
Discussion
Apple Silicon SoC thread
.
In hybrid cpu configuration big cores are there for best per thread performance. If they want still to utilize SMT right core to have it...
Apr 4, 2024
N
naukkis
replied to the thread
Discussion
Apple Silicon SoC thread
.
You do know that what you supposed means disabling HT. Splitting each core to two virtual cores = HT on, one thread per core = HT off...
Apr 4, 2024
N
naukkis
replied to the thread
Discussion
Apple Silicon SoC thread
.
This specially was solutions for utilizing wider cores. Vectorization(SIMD) is working only when there's no dependencies between data -...
Mar 30, 2024
N
naukkis
replied to the thread
Discussion
Apple Silicon SoC thread
.
Many part of loops are't vectorizable but can be unrolled. Compilers do unroll loops to extract parallelism but compile time unrolling...
Mar 28, 2024
N
naukkis
replied to the thread
Discussion
Apple Silicon SoC thread
.
There's something that might give good results from very wide cores that aren't yet utilized - like hardware loop unrolling. Complex to...
Mar 27, 2024
N
naukkis
replied to the thread
Discussion
Apple Silicon SoC thread
.
Everything can be buggy or just doesn't work so usually cpu's have ability to switch off almost all performance options. But loading...
Mar 22, 2024
N
naukkis
replied to the thread
Discussion
Apple Silicon SoC thread
.
The most interesting part of that side-channel is that Apple is using pointer finder in their prefetchers and prefetching suspected...
Mar 22, 2024
N
naukkis
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
Whole NPU meaning is to make optimized hardware for very short datatypes with simplified instructions. FPU does very complex...
Mar 20, 2024
N
naukkis
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
Speculation was about replacing FPU with NPU. FPU doesn't usually even support FP16 math, it's single precision is 32 bit and double...
Mar 20, 2024
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