Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[nicalandia]

After @Kepler_L2 AMD could have 2 layers of stacking of SRAM.

TSMC is capable of more than 6-12 Layers of SRAM Stacking..!! Mind Boggling.... A single CCD in the future might have more than 500 GiB of L3

TSMC Teases 12-High 3D Stacked Silicon: SoIC Goes Extreme

www.anandtech.com

I wonder that when AMD Reaches GiB per CCDs if they will allow the CPU to boot directly from L3 without RAM as Intel did with Knights Landing and Sapphire Rapids. Booting a small Linux Distro(Like SteamOS and running Windows games off L3 should be mind boggling)

 

[Joe NYC]

TSMC is capable of more than 6-12 Layers of SRAM Stacking..!! Mind Boggling.... A single CCD in the future might have more than 500 GiB of L3

TSMC Teases 12-High 3D Stacked Silicon: SoIC Goes Extreme

www.anandtech.com

I don't think TSMC ever demonstrated it in a working product.

And from the AMD little youtube explainer, it did not seem that the approach used in 5800x3d would be extensible to higher layers of stacking.

So looks like AMD now has V-cache, version 2, that has overcome some of the limitations...

And who knows, if it might be able to make it into Zen 4.

In the 2nd part of the tweet, the 9 die GPU, Navi 32 with (4+4) * 16MB = 128 MB of Infinity Cache would be one sweet GPU to get...

Edit: this 9 die configuration would be only 1 level of stacking, never mind...

 

[nicalandia]

I don't think TSMC ever demonstrated it in a working product.

They have plenty of working proof of concept Silicon CPUs. It just happens that the only retail product so far is the 5800X3D

 

[Joe NYC]

I wonder that when AMD Reaches GiB per CCDs if they will allow the CPU to boot directly from L3 without RAM as Intel did with Knights Landing and Sapphire Rapids. Booting a small Linux Distro(Like SteamOS and running Windows games off L3 should be mind boggling)

The MLID video / leak about Mi300 mentions a base die of about 325 mm2, on N6. That could accommodate 1GB of SRAM.

 

[yuri69]

TSMC is capable of more than 6-12 Layers of SRAM Stacking..!! Mind Boggling.... A single CCD in the future might have more than 500 GiB of L3

TSMC Teases 12-High 3D Stacked Silicon: SoIC Goes Extreme

www.anandtech.com

I wonder that when AMD Reaches GiB per CCDs if they will allow the CPU to boot directly from L3 without RAM as Intel did with Knights Landing and Sapphire Rapids. Booting a small Linux Distro(Like SteamOS and running Windows games off L3 should be mind boggling)

The recent Angstronomics RDNA 3 leak mentions using 1-Hi stacked memory while 2-Hi being too expensive.

 

[FangBLade]

Lisa Su said in first presentation of 3d cache that there will be more layers in the future.

 

[Joe NYC]

The recent Angstronomics RDNA 3 leak mentions using 1-Hi stacked memory while 2-Hi being too expensive.

It would have to be relative to how much performance it can add.

And the same incremental cost would have to be compared with another approach to get the same performance increase.

I think AMD will be finding more and ore applications where the trade-off favors stacking.

Also, to keep in mind: N6/N7 was capacity constrained in 2021, and early 2022. These capacity constrains are disappearing. The capacity is being freed up as companies are dealing with inventory correction and economic shocks.

So, it seems, there will be no capacity limits for AMD to introduce the products with V-Cache more widely.

 

[nicalandia]

Lisa Su said in first presentation of 3d cache that there will be more layers in the future.

5800X3D is just the tip of the iceberg. The Future of Computing(weather Personal or HPC) are fully integrated APU: CPU,GPU, Stack RAM, AI on a single cache Coherent Chip

 

[FangBLade]

3dcache would be perfect for APU/gaming laptops, most of them are on 1080p resolutions, and 3dcache works best at that resolution, i hope we will see it next year.

 

[nicalandia]

3dcache would be perfect for APU/gaming laptops, most of them are on 1080p resolutions, and 3dcache works best at that resolution, i hope we will see it next year.

I want a 5 Ghz APU with 3D Cache. RDN3 with GDDR6/HBM2e... One can dream

 

[biostud]

I want a 5 Ghz APU with 3D Cache. RDN3 with GDDR6/HBM2e... One can dream

So next gen Xbox/PS?

 

[nicalandia]

So next gen Xbox/PS?

I am Not allowed to put Unix/Linux on one of those right?

 

[maddie]

TSMC is capable of more than 6-12 Layers of SRAM Stacking..!! Mind Boggling.... A single CCD in the future might have more than 500 GiB of L3

TSMC Teases 12-High 3D Stacked Silicon: SoIC Goes Extreme

www.anandtech.com

I wonder that when AMD Reaches GiB per CCDs if they will allow the CPU to boot directly from L3 without RAM as Intel did with Knights Landing and Sapphire Rapids. Booting a small Linux Distro(Like SteamOS and running Windows games off L3 should be mind boggling)

Surely you mean 500 MB not GB L3.

 

[nicalandia]

Surely you mean 500 MB not GB L3.

Yes, I ment 500 MiB per CCD

 

[LightningZ71]

I am more interested on MT Performance. The AVX512 performance will tip the balance to the 7950X part(as in doubling the AES-XTS Performance of the 13900K)

Because I fully expect the High Clock 32T Zen4 CPUs to beat/match Slow Clock 32T Ice Lake Xeons on AVX512 and the 13900K with it's 32T even at High Speeds can't hold a candle to those slow xeons at AVX512 performance

View attachment 66671

Be prepared for the subscore weight of AES-XTS to be reduced again...

 

[Abwx]

Weight of cryptography is 5%, Integer is 65% and FP is 35%, so even 2x perfs for AES wont move the ST score by much.

 

[nicalandia]

Be prepared for the subscore weight of AES-XTS to be reduced again...

Perhaps...

Intel has all given up on AVX512 for the desktop, Even Early batch Alder Lake Celerons(2C/2T) can beat/match 12900K CPUs in MT cryptography

 

[nicalandia]

Weight of cryptography is 5%, Integer is 65% and FP is 35%, so even 2x perfs for AES wont move the ST score by much.

It didn't for Milan vs Genoa, but in MT it adds up..

By the way Geekbench5 is also another benchmark app that does not take into account any Performance gains by memory subsystem adjustments done a the core level. At least it would seem to fit nice on a 2 MiB L3 per core CPU

 

[Gideon]

Now pretty much confirmed 7950x has a 5.7Ghz ST boost clock and 5.85Ghz XFR (probably needs monster cooling for that though):

https://twitter.com/x/status/1563846926164176901

EDIT:

You have to give credit to anstromics as well, who nailed that boost frequency already in May.

One might argue it was a lucky guess, but the way he writes: no technical illiteracy, no BS about "sources" saying conflicting things. Just relevant facts in great detail.

I'm totally confident in his RDNA3 leak as well.

 

[v.strix]

I am more interested on MT Performance. The AVX512 performance will tip the balance to the 7950X part(as in doubling the AES-XTS Performance of the 13900K)

Because I fully expect the High Clock 32T Zen4 CPUs to beat/match Slow Clock 32T Ice Lake Xeons on AVX512 and the 13900K with it's 32T even at High Speeds can't hold a candle to those slow xeons at AVX512 performance

View attachment 66671

Yeah, it ain't gonna double deleted there...

Just look closer at the 5950X MT AES-XTX results. With 16 cores and 32 threads it barely reaches 2x of ST score! At that point slow clocks and AVXwhatnot doesn't even matter.

The slow and ugly Ice Lake Xeon, on the other hand, has tons of bandwidth on its 8 channels of memory. And that's exactly what this degenerate microbenchmark seems to be measuring here.

I guess, that shouldn't be one bit surprising when it's designed by self-proclaimed chimps.

Please - no profanity in the tech subforums.
admin allisolm

 

[Gideon]

Now pretty much confirmed 7950x has a 5.7Ghz ST boost clock and 5.85Ghz XFR

The near 1GHz frequency jump in a generation is very impressive. AMD didn't get anything near that out of the previous major node jump (Zen 2).

Though I have to give props to Raptor Lake as well. Getting a considerably wider core to clock to 5.8Ghz on a deleted node is also very impressive (even though their starting position was also much higher).

Anyway we just have to see how many Intel can produce (e.g. Will we see the rerun of the 10850K saga of releasing the same chip but slightly lower boost clocks)

No profanity allowed in the tech forums.
admin allisolm

 

[FangBLade]

Yeah, it ain't gonna double shit there...

Just look closer at the 5950X MT AES-XTX results. With 16 cores and 32 threads it barely reaches 2x of ST score! At that point slow clocks and AVXwhatnot doesn't even matter.

The slow and ugly Ice Lake Xeon, on the other hand, has tons of bandwidth on its 8 channels of memory. And that's exactly what this degenerate microbenchmark seems to be measuring here.

I guess, that shouldn't be one bit surprising when it's designed by self-proclaimed chimps.

Hello new user, can you introduce yourself?

 

[DrMrLordX]

(probably needs monster cooling for that though):

I hope "monster cooling" actually does something positive for Raphael. It did very little for Matisse. My loop feels a bit wasted.

 

[Timmah!]

Now pretty much confirmed 7950x has a 5.7Ghz ST boost clock and 5.85Ghz XFR (probably needs monster cooling for that though):

https://twitter.com/x/status/1563846926164176901

EDIT:

You have to give credit to anstromics as well, who nailed that boost frequency already in May.

One might argue it was a lucky guess, but the way he writes: no technical illiteracy, no BS about "sources" saying conflicting things. Just relevant facts in great detail.

I'm totally confident in his RDNA3 leak as well.

since that cpu-z screen shows 4,85 GHz clock, how does that confirm 5,8/5,85 ST clocks?
is that 4,85 all core turbo?

 

[itsmydamnation]

The near 1GHz frequency jump in a generation is very impressive. AMD didn't get anything near that out of the previous major node jump (Zen 2).

Though I have to give props to Raptor Lake as well. Getting a considerably wider core to clock to 5.8Ghz on a shittier node is also very impressive (even though their starting position was also much higher).

4 vs 5 cycle L1D
/we are not the same meme