Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[Doug S]

You realise that this information is behind the paywall? That's not fair to Charlie.

If Saylick is a subscriber (especially if his company pays for it not him personally) then yeah I'd agree. I would assume Charlie requires subscribers agree not to publicly repost information from his articles.

If however Saylick found that information repeated elsewhere by someone else then its fair game, IMHO.

I may be annoyed that all of Charlie's best info is behind a paywall, but he's got a right to make a living.

 

[eek2121]

@scineram that is now how the voting works here.

 

[esquared]

I am going to say this once and once only.

Stop with the the insults.
This is an AMD Zen 4 thread, not an Intel thread.
If you cannot keep your comments to the topic at hand, you will be infracted.

This thread is now locked for the next few hours to get you people to calm down. If you come back here to troll AMD, I will vacation you, so think very clearly before you post.



esquared
Anandtech Forum Director

 

[Hitman928]

It's not incumbent on reviewers to use overclocked memory to make a CPU look better than it actually is. Why should AMD get a pass all of a sudden for using optimized memory, when these websites have been using standardized memory for years in their reviews?

You're making it seem as though these websites are intentionally crippling Zen 4, but that's always been their testing method and they have a right to keep it that way.

As I said in the other thread, Zen 4 has a poor and inefficient memory controller. The benchmarks in the HWUB video show that Raptor Lake is significantly faster than Zen 4 when both are using DDR5 5200. That actually surprised me, as I genuinely wasn't aware how large the gap was and how suboptimal the memory controller was in Zen 4. Even with DDR5 6000, Zen 4 requires tight primaries to really catch up with Raptor Lake.

This sort of thing brings up issues of fairness in reviews. I personally don't care whether reviewers use overclocked memory or not, but I do care if they optimize the memory for one platform more than the other. Zen 4's optimal memory config may be DDR5 6000 with tight timings, but RPL's can go much, much higher.

This is just more gaslighting.

Some reviewers have been using only officially supported memory the whole time, but many switched to using overclocked memory many years ago once XMP (and similar) memory became a thing, long before the Zen architecture was even a rumor.

Techspot 4790k review using overclocked memory. 9 years ago.
TPU 4790k review using overclocked memory. 9 years ago.
TPU 3770k review using overclocked memory. 10 years ago.
Techreport 4790k review using overclocked memory. 9 years ago.

From Zen 1 (released 6 years ago now) and for every iteration after, it has been known that the Zen architecture benefits more from faster memory speeds. This isn't because their memory controllers are "weak" (outside of maybe Zen 1) but because of their chiplet design which introduces additional latency as well as how the memory system on the CPU is dependent on the infinity fabric clock which is dependent on the memory speed. The reason why people with no agenda don't care about gaming tests at dog slow memory speeds is because no one builds a gaming computer with dog slow memory speeds today (EXPO/XMP memory is easy to find and relatively inexpensive if you don't go too high in speeds). So while those reviews provide valid data, it's not really that useful and you seem to be the only one calling out reviewers as being stupid or biased because they don't show the results you think they should.

As far as how fast of memory to run, RPL can go above DDR5-6000, but so can AMD. RPL can go significantly higher, but there are already tests showing that its performance stops scaling well below it's fastest speeds. You have to draw the line somewhere but what it really boils down to is that you'll always find fault in the reviewer's choices if the results show the Zen chips get too close to RPL for your liking, no matter if their reasoning is valid or not.

 

[Det0x]

Allegedly first results for Dragon Ridge

AMD strikes back: Ryzen 9 7945HX beats Intel Core i9-13980HX despite much lower power consumption - NotebookCheck.net News

Did AMD just win the mobile CPU Game? - AMD Ryzen 9 7945HX + Zephyrus Duo 16 Hands-On - YouTube

Edit: added the video from the same source

Intel's flagship consumed anywhere from 180-190W and even spiked beyond 200W with average temperatures hovering around 85C. Within a few seconds of operation, the CPU was throttling to sub 3.8 GHz clocks. Meanwhile, AMD's chip never broke past 120W which was its peak and temps were close to 80C but the chip remained steady with a 4.3-4.4 GHz clock speed.

 

[NostaSeronx]

That is the embedded roadmap though.

EPYC:

https://www.amd.com/en/processors/epyc-7002-series

Embedded EPYC:

https://www.amd.com/en/processors/embedded-epyc-7002-series

It isn't saying Milan should have been 2020Q3-2021Q2;

https://www.amd.com/en/processors/epyc-7003-series

It is saying Embedded Milan should have been 2020Q3-2021Q2;

https://www.amd.com/en/processors/embedded-epyc-7003-series

Also, effectively the google date the Embedded website is Aug 4, 2020

https://www.amd.com/en/products/specifications/embedded/17211

Was only listed on: Aug 5, 2020.

Meaning that the Embedded Epyc 7001/7002 only launched then in August 2020.

https://www.aicipc.com/image/images/webinars/AMD%20Presentation.pdf

Jan 19, 2021 upload date
Googling it with "V3000"/"Zen4"/"7004" points it to having the slide.

Identifying the asterisk:
*AMD roadmaps are subject to change without notice or obligations to notify of changes.
Placement of boxes is not intended to represent first year of product shipment.

 

[eek2121]

It would not be unexpected, if in the end Zen4 support only DDR5 memory.

https://twitter.com/x/status/1482418526854033410

No DDR3 or DDR2 or DDR support either…

 

[itsmydamnation]

Chu
Chiphell is pretty accurate..

What chips has the author created to lecture what intel AMD has is createding lol ?

 

[Saylick]

.....only for Turin-X to roll up....

Intel: Why do I hear boss music? 😨

😂🤣

 

[uzzi38]

I'm kinda disappointed nobody seems to have really thought about what AMD talked about with regards to Zen 4C honestly.

Same ISA support, same IPC, and now also confirmed to use half of the core area (key word being core, mind you).

That puts Zen 4C in similar size regions to ARM cores such as V1. That's kind of a big deal.

Also entirely unrelated sidenote but:

https://twitter.com/x/status/1564858445546807297

I did warn you guys. For Raphael vs Raptor Lake the issue isn't power consumption, it's cooling. Thermal density is not a fun thing.

 

[leoneazzurro]

I can't say I am impressed with Zen 4 Desktop SKUs.
Zen4 SKUs released by AMD are less energy efficient than their predecessors even though they are on 5nm. High clocks are simply killing any efficiency gains from the process.
Ryzen 5 5600X vs Ryzen 5 7600X -> 65W vs 105W (+62%)
Ryzen 7 5700X vs Ryzen 5 7700X -> 65W vs 105W (+62%)
Ryzen 9 5900X vs Ryzen 5 7900X -> 105W vs 170W (+62%)
Ryzen 9 5950X vs Ryzen 5 7950X -> 105W vs 170W (+62%)
I am more interested in model without X in their name and back to 65 and 105W TDP.

If you consider "energy efficiency" simply as a measure of the total energy consumption of a CPU, sure, but the common understanding about "energy efficiency" is perf/W and at the moment we have no data to say it got worse, instead we have AMD's claims (which turned out fairly accurate in the past) of the exact opposite. Let's also not forget that big part of this is also due first to to Intel raising their power consumption a lot in order to be competitive with the top AMD models, because many users look only at pure performance without considering how that performance is obtained. Of course is also Intel's merit to have created a hybrid architecture that is more competitive for the lower end (due to more cores in the form of Gracemont, mainly) forcing AMD to raise clocks on the lower SKUs. It will be interesting to see what happens in two years, when Zen5 lands, and that from current leaks is supposed to be something like an hybrid architecture too.

 

[amrnuke]

It is time to push efficiency charts in the foreground. Problem solved.

Sure, then everyone will complain about the lack of progress in performance. Then you have to push performance charts to the foreground. Rinse. Repeat. (Kidding, of course...)

Zen is not marketed to the public for efficiency, it's marketed for performance. How do you think people would be reviewing the product if AMD chose to instead limit power draw and ended up being just equal to Alder Lake, in the name of efficiency? Seems to me it would be bad publicity, especially with Rocket Lake not even released yet.

 

[MarkPost]

7600X vs. 13600K - 54 Game Benchmark | TechSpot

GPU: 4090
MEM: 6000 (7600X) - 6400 (13600K)





13600K vs 7600X | Jarrod'sTech

GPU: 4090
MEM: 6000




13700K vs 7700X | Jarrod'sTech

GPU: 4090
MEM: 6000




13900K vs 7950X | Jarrod'sTech

GPU: 4090
MEM: 6000

 

[biostud]

Well, sometimes the data is faulty.

https://twitter.com/x/status/1624740626406289408

 

[Racan]

This is what happens when you pair Zen 4 with slow ram.

From these results I expect that the 3D cache will help Zen 4 a lot. If only they could clock as high...

Also explains the garbage gaming performance results from sites like computerbase and pcgameshardware who use DDR5 5200 for Zen 4.

 

[exitorious]

So I used the tweaked ddr5 6000 memory settings from Hardware Unboxed with my 7950x and compared them to my 13900k with ddr5 7200 and the 7950x at regular xmp ddr6000 speeds with both systems using a Geforce 4090 with dlss 3. The lows went up 15 fps in Cyberpunk for the 7950x and match the 13900k now.




Red Dead 2 results with dlss. Lows increased some, so now they match the 13900k. Average is about the same tweaked or not:





I also tested Borderlands 3, it went up 10fps from the memory tweaks on the 7950x.

 

[Mopetar]

sonuds like the new chipset driver was not tested. That may result in what, some non-cache-sensitive games still use V-cache cores?

https://twitter.com/x/status/1629116333991272449

Ooo... Last hype train leaving the station. Last hype train! All aboard!

 

[Joe NYC]

Nice new details. Primarily on V-Cache, but a lot of info on process nodes, die sizes transistor density.

On V-Cache, it has incredible transistor density, even though it stayed on N7. Die size shrunk from 41 mm2 to 36 mm2, number of transistors remained the same but TSVs are more efficiently and densely placed.

Only signal TSVs in the L3 area and power TSVs now segregated and moved over to the L2 area. So the V-Cache now covers L3 and partially L2 as well.

There is also some info on IO dies for both server and client. Graphics is taking quite a bit of space, but that's space on N6 that does not have to use N5.

The V-Cache bandwidth increased from 2 TB/s to 2.5 TB/s and the overhead to access V-Cache is 4 clocks - which is not bad for L3. Also, AFAIK, this overhead is only applicable if the data is coming from V-Cache portion of L3, not all of L3 (from comments going back to 5800x3d).

AMD Shares New Second-Gen 3D V-Cache Chiplet Details, up to 2.5 TB/s

New images of the I/O Die, too.

www.tomshardware.com

 

[coercitiv]

if Nosta is to be believed at all

Name one process & architecture combo "leak" that Nosta talked about in the past and turned out to be true. The amount of fantasy nodes and architectures is staggering, and yet people still eat this crap with a spoon.

You would have better chances at predicting the future of AMD products by tossing a coin. My cat would have better chances of predicting AMD product & node mix, and I don't have a cat. It's still better than what Nosta predicts because me getting a cat and using it to make predictions is still within the realm of possibility in this universe.

 

[KOMACHI_ENSAKA]

Afaik, Trento/Badami is Zen3 (SP3/SP3r4), but it will support Next Gen PCIe/Next Gen IF for unified memory...etc with Frontier and more. So It will lead to A+A (Trento or later + MI200 or later) BIG APU Mode.
(Also, someone said that there is an HBM2 die in Trento, but I don't believe it.)

 

[Hans de Vries]

What's most surprising to me is the I/O die. I'm really not at all surprised by the CCDs if I'm honest, but the I/O die - new nodes have little to know effect on analog circuit density, and Genoa has a very significant increase to I/O (12ch DDR5, 128 PCIe5 lanes etc etc), yet despite that, the I/O die is actually smaller than Rome's.

The physical I/O of 7nm Cezanne is quite small. The 128 bit bus is just 5% of the 180mm2 die (The top-right rectangle) or 9 mm2.



This makes me think that AM5 may jump over Alderlake's 1700 pin package to 2000+ pins (from 1331 for AM4)
It would make desktop motherboards with 4 memory slots, each with its own channel.

AM5 needs to support 3nm CPU's and APU's. Two channel LPDDR4-4266 is already exhausted by 8 VEGA compute units. (Rembrandt has 12 Navi2 compute units on 6nm). The 5nm Rafael has an unknown amount of Navi3 compute units on AM5 and they could be clocked north of 3GHz.

 

[Makaveli]

Ryzen follows a 15-18 month cadence. Warhol is a new core, not an XT style refresh. Warhol and Alder Lake will both likely pop out Q1 2022.

I believe warhol will be an AM5 release to get the chipsets ready and tested for Zen 4. This way they get to iron out any quirks.

 

[NostaSeronx]

Feb 2021+ product bring up.

I can only find GPUs and one other IP bring ups so far with CPUs being less exact:
Vega10 bring up: Jan 2017-April 2017 => August 2017 launch
MI50/MI60 bring up: Jan 2018(start month) => November 2018 launch
Navi10 bring up: July 2018+ => July 2019 launch
PCIe 4.0 bring up in client/server: September 2018+ => July/August 2019 launch
Fiji bring up: Sept 2014 - November 2014 => June 2015 launch
Ontario bring up: 2010(no exact month) => January 2011 launch
Mullins bring up: 2013(no exact month) => April 2014 launch
Kaveri bring up: August 2013 => January~June 2014 launch
Radeon Pro 560x bring up: 2017(no exact month) => July 2018 launch
Radeon Pro Vega bring up: 2018(no exact month) => November 2018 launch
MI100 bring up: July 2019+(no exact start) => November 2020 launch
Zen SoC/Server (Zeppelin) bring up: Before August 2016, After November 2015 => March 2017 launch
MI200 bring up award: December 2020 => not yet launched.
3 launched within the year of first bring-up mention.
9 launched the year after first bring-up mention. Of those, majority of the mentions are during the later half/second half of the year.

On DDR-side LPDDR5/DDR5 has two spots of bring up: January 2020+ and July 2020+.

So, Raphael launching earlier than expected is more likely. ¯\_(ツ)_/¯

 

[dnavas]

An 18 months release cycle would put Zen 4 to Q2 2022. However, Zen 4 brings a brand new platform with DDR5/PCIe5. So delays are to be expected.

I'm personally finding it increasingly difficult to justify investing in a pcie4 TR platform purchase, so I hate what this does for Zen4 TR, but it frankly doesn't make sense to ship a DDR5 platform prior to DDR5 being available in quantity. So yes, I'd expect later than sooner.

Unless [I add, somewhat self-servingly] you release on the platform that's already more expensive and might be more willing to absorb the cost. I don't expect AMD is doing this, but it seems like it would make some sense to put the TR chiplets after desktop, so that desktop can bake the design, but put the TR IO on the bleeding edge. You allow TR to benefit from the choice of the best chiplets, and allow the desktop to benefit from the better/cheaper supply chain of parts.

 

[DisEnchantment]

I'm pretty sure since Zen2/3, AMD has been using the most dense libs available.

Ex:
View attachment 44460

The actual design reasons for AMD going for Hi-Freq, rather than going full on Hi-Inst will probably remain unknown. For all we know it could be marketing-sided rather than engineer-sided. As it is psychologically easier to sell a chip that has increased frequency over the last generation.

https://images.anandtech.com/doci/14525/Mike_Clark-Next_Horizon_Gaming-CPU_Architecture_06092019-page-018.jpg

Above, extended w/ actual high-end on AMx:
Ryzen 7 1800X = 4.1 GHz boost
Ryzen 7 2700X = 4.3 GHz boost
Ryzen 7 3950X = 4.7 GHz boost
Ryzen 7 5950X = 4.9 GHz boost

Zen3 is using N7 HD indeed. While RDNA is using N7 HP.
For N5 the most optimal range for Zen 4 would be around 3.8-4.2 GHz according to the Shmoo plot, after that would need considerable jump in voltage for getting the frequency to the same levels like 5950X for example.
One of the advantages of designs which top out at ~3.2 GHz is that they are well below this value resulting in big gains in efficiency.

Why doesn't AMD use the high density process? Wouldn't the much higher IPC made possible by many more transistors make up for the lost frequency? Plus, it would be much more energy efficient

My thinking is that when they originally designed Zen1-Zen3 using the CCX concept they intended it to be very small and easily manufacturable. It was supposed to be cheap to produce. The high clocks could help get more performance.
Zen3 Core and upto L2 is quite small in comparison to most contemporary designs. Zen3 core (without L3) is less than half the MTr of M1
However when Zen2 and later Zen3 landed they need to tack on the big L3 to handle the weakness of the memory hierarchy with the multiple CCXs
In the end Zen3 got big anyway. Also making the MTr or the active core too high while operating in high frequency would have increased the TDP by a bit

For Zen4 with this learning it should be interesting if AMD would raise the transistor count drastically or again stick with smaller core.