Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[Ajay]

It seems to be in progress. Samsung announced 512 GB DIMM with 8 layers of memory stacked:
Samsung Teases 512 GB DDR5-7200 Modules (anandtech.com)

Interesting, thanks!

I'm really curious about the memory IF for Zen4. With faster DDR5, it seems unlikely that boards will be able to run 1:1 anymore.

 

[Ajay]

None of us knows the real reason behind the changed HEDT plans. The speculation is totally fine and also really interesting, but the whole forum seems to make judgments along these pure speculations...

Yeah, that's a real head scratcher. Not all of us buy into every rumor that floats around. That said, it's often all we have now a days. Public guidance from AMD, Intel, etc. is far more limited than it was a decade ago (and two decades ago these companies were almost transparent compared to today). After years of resisting, I'm even following some of the better 'leakers' just hoping to have some clue as to what is going on. It's not a fun time from that perspective.

 

[Joe NYC]

So if zen4 does not launch with 3Dcache, do you think it will be a regular part of the AMD launch CPU cycle?

zen3
zen3+3Dcache
zen4
zen4+3Dcache?
...
...

Genoa Zen 4 seems to be ready before the N5 stacking is enabled, so my guess is that Genoa will follow that path.

Rafael - if it launches late 2022, stacking may already be available by then. If it launches earlier, say mid 2022, it may be as you describe.

Edit, looks like @DrMrLordX said virtually the same just above.

 

[moinmoin]

None of us knows the real reason behind the changed HEDT plans.

May well be the case that unlike for server, mobile and desktop (in that order) AMD never had a concrete plan for the HEDT niche to begin with. Remember back when Threadripper was revealed it was literally publicly showcased as a side project of a couple of guys. Seems logical that that area lacks planning and firm roadmaps then.

 

[Roumaldo]

How much cores do you think that will have the Ryzen 7000? We will see a octa-core for the hipotetic 7600X? 10 core for the 7700X? 12 core for the 7800X? 16 for 7900X and 24 for the 7950X? A six-core for a hipotetic 7500? Make your bets!

 

[jamescox]

Interesting, thanks!

I'm really curious about the memory IF for Zen4. With faster DDR5, it seems unlikely that boards will be able to run 1:1 anymore.

I assume that going 6 nm, or at least something more advanced than GF 12 nm, should allow them to increase IO die clock speed. If they have an integrated GPU, then they need to use a process that can deliver reasonable clocks and power consumption for the GPU. If the IO die is derived from the same design as Epyc, which has triple channel memory per quadrant, then it may have wider internal interconnect to support that, even if they don’t route all 3 channels through the AM5 socket.

 

[jamescox]

May well be the case that unlike for server, mobile and desktop (in that order) AMD never had a concrete plan for the HEDT niche to begin with. Remember back when Threadripper was revealed it was literally publicly showcased as a side project of a couple of guys. Seems logical that that area lacks planning and firm roadmaps then.

I am kind of wondering if there will be a Threadripper based on SP5. It will be a very expensive socket. It would be nice if they had a half size socket for HEDT and workstation use, but it seems like they aren’t going that route. A smaller, cheaper socket with just 6 channel memory and 64 high speed serdes would be good, but it is a lot of work for a very small market. An SP5 board and cpu package will be very expensive, even if it only has half the circuits IO routed. They could move AM5 up a bit by allowing up to 3 memory channels and and up to 3 cpu chiplets. That would narrow the very wide gap between AM5 and SP5 a little bit.

 

[Vattila]

Since rumours seem to indicate that the Ryzen 6000 series will be based on Zen 3+, and Zen 4 will arrive in the 7000 series, I have updated the thread title.

AMD Ryzen 6000U 'Rembrandt' APU Shows Up With DDR5 Memory Support In ASUS's Next-Gen Vivobook, Faster Than Ryzen 7 5800U

ASUS's next-gen laptops with AMD Ryzen 6000 Rembrandt APUs have once again leaked out and this time over at the BAPCo benchmark repository.

wccftech.com

Let me know if WccfTech has got it wrong.

 

[DrMrLordX]

Since rumours seem to indicate that the Ryzen 6000 series will be based on Zen 3+

Wouldn't an AM4-based "Zen3+" CPU (NOT APU) be Warhol? Which was supposedly cancelled months ago?

 

[Topweasel]

Wouldn't an AM4-based "Zen3+" CPU (NOT APU) be Warhol? Which was supposedly cancelled months ago?

I thought Zen 3+ was less of slight process difference (like Zen+) and just clock speed refresh? If so couldn't it just be that they are going to use Zen3d for the refresh? I mean its a product line with only 6 shipping and only 4 public products. There is a lot of assumptions that the 5600x and 5800x wouldn't get 3d cache adds.

Or maybe like 4000 series, 6k will be mobile only. It would make sense considering its more important for their OEM sales that they refresh that more often.

Edit: Just realized that Zen 3+ is 6nm Zen 3. So probably increases the chances that because Zen 4 isn't launching till the end of the year, that 6000 series will probably be mobile only.

 

[Thibsie]

I see ryzen 6xxx as:
Zen3+ APU 6nm & Zen 3/vcache 7nm

 

[Topweasel]

I see ryzen 6xxx as:
Zen3+ APU 6nm & Zen 3/vcache 7nm

I just don't see it. They caught a lot of flack for model number not really reflecting generation. I can understand why they did what they did for the 5700u and 5500u, but I doubt they push that boundary much more than that. Though it will be more acceptable if they don't have a desktop version of the APU. The Zen3d stuff is a little weird I can see it being a refresh, but on the other hand I can't. In programs that will use more cache it will be wonderful, for ones that don't it will perform exactly the same. I can't see it being a new gen, more of an alternative for people who can use it. Though chances are warhol got canceled because Zen3d saw more increases in performance then Zen 3+.

 

[DisEnchantment]

A few interesting patents/applications from AMD that I feel could help with improving overall OoO window and the front end decode and dispatch (besides straight up increasing the resources themselves)

• Retire queue compression
○ From https://www.freepatentsonline.com/11144324.html
Fusing multiple uops in one entry in the ROB. Could increase effective ROB size without increasing the number of entries

• Branch target buffer compression
○ From https://www.freepatentsonline.com/10592248.html
Multiple branch targets fused in one entry

• Implementing a micro-operation cache with compaction
○ From https://www.freepatentsonline.com/11016763.html
uop cache compression could help increase the uop cache within the same footprint

• Filtering Micro-Operations for a Micro-Operation Cache in a Processor
○ From https://www.freepatentsonline.com/y2021/0334098.html
Implementing a filtering mechanism to filter out insignificant uop or non recurring uops

• METHODS AND SYSTEMS FOR UTILIZING A MASTER-SHADOW PHYSICAL REGISTER FILE
○ From https://www.freepatentsonline.com/y2021/0357222.html
Implementing dual PRF banks and switching the PRF bank for the uop in flight when it they are not ready to retire. Assuming a lot of uops are not single cycle, this could increase the available entries in the PRF

• METHOD AND APPARATUS FOR VIRTUALIZING THE MICRO-OP CACHE
○ From https://www.freepatentsonline.com/y2021/0149672.html
Using conventional cache cache as a backup storage for evicted uop reducing the decode

 

[Tuna-Fish]

• METHODS AND SYSTEMS FOR UTILIZING A MASTER-SHADOW PHYSICAL REGISTER FILE
○ From https://www.freepatentsonline.com/y2021/0357222.html
Implementing dual PRF banks and switching the PRF bank for the uop in flight when it they are not ready to retire. Assuming a lot of uops are not single cycle, this could increase the available entries in the PRF

If I understood this patent correctly, what they are actually doing is replicating the PRF, with the "shadow" having only very limited read ports, and then pushing all the old results from the "master" PRF to the same register number in "shadow" if/when their ARN is rewritten after speculation. After that point, the only situation where they will ever be used is if the speculation failed, in which case they can be copied back to the master on top of the current results, because by definition those new results are all garbage, and this can be done through very limited read ports without performance degradation because the CPU is currently stalled waiting for replacement instructions to bubble up to the execution units.

A neat trick, up to doubling the effective size of their PRF while keeping size/power down (because a register with a single R/W port is way cheaper to make than multi-ported registers).

 

[soresu]

I just don't see it. They caught a lot of flack for model number not really reflecting generation.

4xxx -> 5xxx brought a CPU µArch upgrade for APU and discrete CPU SKUs.

5xxx -> 6xxx will bring a (long overdue) GPU µArch and CU count upgrade for APU and a v-cache upgrade for discrete CPU SKUs.

Both of which will bring significant performance gains.

I don't see the problem so long as Zen4 SKUs don't use Ryzen 6xxx at all.

 

[Topweasel]

It's not that fluid and you just need to look at the 5700U and 5500u to realize they don't even always follow their own playbook. But the move to straighten level out the APU model name was the flack they took with the 3k APU's and laptop chips having a much slower Zen+ core than the 3k desktop CPU's. The Desktop APUs being the worst of it.

They aren't going to have as un-even a lineup again. Especially with the 3d cache being very program specific in its performance boosts. Tons of applications won't see any improvement.

 

[jamescox]

I see ryzen 6xxx as:
Zen3+ APU 6nm & Zen 3/vcache 7nm

How would that work specifically? Would the Zen 3+ parts be the regular models and the Zen 3 X3D parts be the ‘X’ models? If Zen X3D is 7 nm, then it might be lower clocked than 6 nm Zen 3+ unless they only sell top bin parts with Zen 3 X3D. It still seems bad to have a completely new major model number just for a clock speed bump, so I am wondering if Zen 3+ will either have more improvements or if they will just be sold as 5000 XT parts.

 

[moinmoin]

Would the Zen 3+ parts be the regular models

They are APUs, so they'd go with U/H/G.

 

[Thibsie]

That's it:

• Zen3+ APUs (rdna2) monolithic 6nm
• Zen3D. Usual Zen3 7nm but with Vcache

 

[jamescox]

That's it:

• Zen3+ APUs (rdna2) monolithic 6nm
• Zen3D. Usual Zen3 7nm but with Vcache

Okay, if the Zen3+ APUs will be for everything less than 8 cores, then this is something that I have expected and talked about for quite a while. That would significantly reduce the number of Zen X3D chiplets that they need for desktop if they are only for 12 or 16 core models. I guess they may do an expensive 8 core also. Everything below that gets an APU.

 

[eek2121]

I'm actually rather curious now. Are there any (very) recent leaks on Rembrandt L3 cache sizes? Poking at a rumor I heard regarding a product repositioning @ AMD. I know this is a Zen 4 thread, but this relates directly to Zen 4...which is why both Future Intel and AMD threads should all be consolidated, IMO.

 

[LightningZ71]

Rembrandt appears to be an overhaul of the iGPU side of things more than anything. I suspeat that they might use the density improvevent of N6 to double the L2 cache, but that would involve re-floorplanning the CCX, and that's a lot for such a small change.

 

[uzzi38]

Rembrandt appears to be an overhaul of the iGPU side of things more than anything.

DEAD WRONG.

Literally everything but the CCX has been touched up, and many of those improvements matter far more in the grand scheme of things than the iGPU improvement.

 

[Thibsie]

DEAD WRONG.

Literally everything but the CCX has been touched up, and many of those improvements matter far more in the grand scheme of things than the iGPU improvement.

Curious about what those are.

 

[Gideon]

DEAD WRONG.

Literally everything but the CCX has been touched up, and many of those improvements matter far more in the grand scheme of things than the iGPU improvement.

I can't wait to see how this will affect battery life among other thinds (is Rembrant 6nm as well?) .

Certainly a much needed change, considering Cezanne was essentially Renoir with the CCX replaced and L3 doubled. There hasn't been much change to the uncore for 2 years.