Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[DrMrLordX]

Cinebench doesn't benefit from large L3 at all.

I know, that's why I wanted them to run it. TBH I didn't think Blender did either!

 

[randomhero]

Since we had no post speculating Zen4 performance for a long time, here is one.

After seeing several Zen3+ reviews and few rumours of Zen4 layout and possible "IPC", I am strogly inclined to that Zen4 could have 30% higher single thread performance and 50% higher multithread performance than Zen3.

 

[deasd]

https://twitter.com/x/status/1512740987927293955

at the meanwhile:

 

[nicalandia]

I don't know if this is an actual picture or if someone made a 3D render/print with known information, but it checks out in every aspect.

After The SP5 Socket, AMD's EPYC Genoa CPU With 12 Next-Gen Zen 4 CCDs on 5nm Node With Up To 96 Cores Pictured

AMD's 5nm Zen 4 powered EPYC Genoa server CPU has been pictured in its full-fat 12 CCD configuration for the SP5 server platform.

wccftech.com

 

[randomhero]

https://twitter.com/x/status/1512740987927293955

at the meanwhile:

View attachment 59749

Wasn't Greymon55 recently twitting about packaging facilities being ready for Zen4?

So, is this mass production in fab or mass production of final product??

Could someone with Twitter account ask him for further clarification?

 

[deasd]

Wasn't Greymon55 recently twitting about packaging facilities being ready for Zen4?

So, is this mass production in fab or mass production of final product??

Could someone with Twitter account ask him for further clarification?

I think, no need to ask..... 'mass production' always has 3-6 months before a product release, and I don't think he knew that lot, from his tone I guess he's just a second hand source though..,,, after all it's safe to do Zen4 release countdown now. ticktockticktock

 

[jpiniero]

I don't know if this is an actual picture or if someone made a 3D render/print with known information, but it checks out in every aspect.

That does look like a render.

Talked about this in the other thread but... TSMC is getting more expensive (and not less as you would normally expect) over time. Going from a cheap GloFo IO die to N6 is going to be costly. DDR5 is going to be pricey for awhile. Unlike the GPUs I don't think you can convince Intel to jack up their prices as well.

Not sure how AMD is going to reconcile this but only selling Ryzen 7 and above might be what they end up doing.

 

[randomhero]

I think, no need to ask..... 'mass production' always has 3-6 months before a product release, and I don't think he knew that lot, from his tone I guess he's just a second hand source though..,,, after all it's safe to do Zen4 release countdown now. ticktockticktock

That is the reason why I asked. If it starts mass production in packaging facilities then we can expect Zen4 on shelves in August, if it is in fab then November.

 

[nicalandia]

That does look like a render.

Talked about this in the other thread but... TSMC is getting more expensive (and not less as you would normally expect) over time. Going from a cheap GloFo IO die to N6 is going to be costly.

GloFo 14nm/12nm must be really inefficient as to go for the more expensive 6nm IO Die, I guess they tested the 14nm/12nm IO die and the TDP got out of hand real quick with 12 CCDs

 

[Abwx]

I think, no need to ask..... 'mass production' always has 3-6 months before a product release, and I don't think he knew that lot, from his tone I guess he's just a second hand source though..,,, after all it's safe to do Zen4 release countdown now. ticktockticktock

6 months is way too long, they may stockpile a given quantity for the surge in sales at the start, but they wont wait to have 3 months sales inventory.

More likely that they ll announce the product at Computex with availability a month later.

 

[tomatosummit]

GloFo 14nm/12nm must be really inefficient as to go for the more expensive 6nm IO Die, I guess they tested the 14nm/12nm IO die and the TDP got out of hand real quick with 12 CCDs

14/12 was already very inefficient where most people agree that the rome io dies chews up ~100w.
Genoa has almost 50% extra io running at higher speeds and while the new standards are more efficient per bit, overall power draw goes up.
Adding to that I don't know if there are pcie5 and ddr5 blocks available on 12lp.

N7 nodes are more expensive but the amount of silicon used will be significantly reduced, especially since a 12nm die would be going over 500mm^2 and into worse yields, so it might be more like a sidegrade in cost for amd more than a huge increase.

 

[nicalandia]

N7 nodes are more expensive but the amount of silicon used will be significantly reduced, especially since a 12nm die would be going over 500mm^2 and into worse yields, so it might be more like a sidegrade in cost for amd more than a huge increase.

The IO Die is about the same size (416 mm^2 in 12nm vs 397 mm^2 6nm)

 

[DisEnchantment]

N7 is going to be 5 years in 2H2022, and N6 provides substantial cost benefit over N7 (TSMC's statement).
Capacity is not contested and TSMC has a ton of capacity for it, around 250K wpm. And wafer cost should be far better with such a long time to amortize the initial fab costs.

I would not be surprised if it is more economical having everything on N6 at this point.
Reuse of many proven hard macros can be done, no need to design the same thing for 12LP and N6, N7, N5 etc.,
A whole slew of blocks are already hard proven on N7/6, memory controllers, PHYs, GPU blocks, putting them in an N6 cIOD is not going to require much design and validation effort.
On GF 12LP there would a whole bunch of things to redo newly like RDNA2 block and others as mentioned.

 

[jpiniero]

N7 is going to be 5 years in 2H2022, and N6 provides substantial cost benefit over N7 (TSMC's statement).
Capacity is not contested and TSMC has a ton of capacity for it, around 250K wpm. And wafer cost should be far better with such a long time to amortize the initial fab costs.

RIght now N7 costs more than it did 2 years ago. And it's all taken.

 

[eek2121]

View attachment 59757
N7 is going to be 5 years in 2H2022, and N6 provides substantial cost benefit over N7 (TSMC's statement).
Capacity is not contested and TSMC has a ton of capacity for it, around 250K wpm. And wafer cost should be far better with such a long time to amortize the initial fab costs.

I would not be surprised if it is more economical having everything on N6 at this point.
Reuse of many proven hard macros can be done, no need to design the same thing for 12LP and N6, N7, N5 etc.,
A whole slew of blocks are already hard proven on N7/6, memory controllers, PHYs, GPU blocks, putting them in an N6 cIOD is not going to require much design and validation effort.
On GF 12LP there would a whole bunch of things to redo newly like RDNA2 block and others as mentioned.

It is known that TSMC is charging significantly less for N6. than they are for N7, at least for some customers.

 

[nicalandia]

It is known that TSMC is charging significantly less for N6. than they are for N7, at least for some customers.

Why? did they overestimate the demand and would rather break even than lose the investment?

 

[jpiniero]

It is known that TSMC is charging significantly less for N6. than they are for N7, at least for some customers.

Yeah I doubt that.

 

[DisEnchantment]

RIght now N7 costs more than it did 2 years ago. And it's all taken.

I don't think wafer contract for products using N6 will use seasonal price fluctuation from 2H21-1H22 when the products in question run all the way to 2024 and beyond. Of course AMD is not buying wafers quarter by quarter. Back then N5 capacity was less than 60Kwpm, in H2 this year it will be 150K wpm and N3 is coming online too in H2 this year (F18P5 and P6 should be able to provide 60K wpm by end of the year).
QCMM, NVDA, AAPL, MTK (and AMD too) which accounts for 70+% of the wafer share of leading edge wafers are migrating to N5 and N4 for a large portfolio of their products.

 

[jpiniero]

I don't think wafer contract for products using N6 will use seasonal price fluctuation from 2H21-1H22 when the products in question run all the way to 2024 and beyond. Of course AMD is not buying wafers quarter by quarter. Back then N5 capacity was less than 60Kwpm, in H2 this year it will be 150K wpm and N3 is coming online too in H2 this year (F18P5 and P6 should be able to provide 60K wpm by end of the year).
QCMM, NVDA, AAPL, MTK (and AMD too) which accounts for 70+% of the wafer share of leading edge wafers are migrating to N5 and N4 for a large portfolio of their products.

N5 is more expensive too. I think it's "discounts" that TSMC took away which is how the price hike happened. Not sure though.

AMD can absorb it fine, they just have to raise prices.

 

[maddie]

RIght now N7 costs more than it did 2 years ago. And it's all taken.

I thought that TSMC is actively encouraging customers in migrating to N6 from N7? Could this be a factor? In any case N6 is cheaper.

 

[leoneazzurro]

The IO Die is about the same size (416 mm^2 in 12nm vs 397 mm^2 6nm)

Yeah but these are not same functionality, you have DDR5 now, PCIE-5, and more chiplets to connect (12 instead of 8). So yes, die size is almost the same but Xtors are likely to be WAY higher. So doing it in 12nm would have been at reticle limit or so, not exactly cheap either.

 

[jpiniero]

I thought that TSMC is actively encouraging customers in migrating to N6 from N7? Could this be a factor? In any case N6 is cheaper.

It might still be cheaper per transistor. The wafer cost almost has to be the same or more than N7. You probably also get more wafers.

 

[Doug S]

It might still be cheaper per transistor. The wafer cost almost has to be the same or more than N7. You probably also get more wafers.

Why would the wafer cost be higher for N6? The whole point of creating it was to increase wafer throughput so TSMC could run more wafers with the same equipment. They would have introduced N6 even if there was no shrink at all. I can't imagine how N6 couldn't be cheaper for TSMC per wafer than N7. Remember, N7 was not designed for low cost it was designed for low risk by not using EUV at all. Once they became comfortable with EUV N7 no longer served any purpose except to allow stuff designed for it to continue to be made on it. N7+ was created for customers who were willing to wait a bit to get a cheaper version of N7. N6 is an even cheaper version of N7+.

If they could force all their N7 customers to use N6 they would, but since they can't the next best thing to is to collect at least enough additional money per wafer to offset TSMC's higher cost. And the fewer N7 wafers they run the larger the gap between N7 and N6 prices is likely to be - whether that's by further increases in N7 prices, decreases in N6 prices, or both, who knows.

 

[jpiniero]

Why would the wafer cost be higher for N6? The whole point of creating it was to increase wafer throughput so TSMC could run more wafers with the same equipment. They would have introduced N6 even if there was no shrink at all. I can't imagine how N6 couldn't be cheaper for TSMC per wafer than N7.

Cheaper per transistor, not cheaper per wafer. And there's no guarantee that TSMC would pass on any cost savings on now, given the price hikes.

 

[Tuna-Fish]

Cheaper per transistor, not cheaper per wafer. And there's no guarantee that TSMC would pass on any cost savings on now, given the price hikes.

It's also cheaper per wafer. N6 requires less steps on some of the machines that are a production bottleneck, they can push out substantially more N6 wafers out of the same plant.