Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[biostud]

I am not sure if AMD would like to go that route. There was an article by Puget System about memory channel performance. 8 Memory Channels gives trample 4 channels all day long.

• AMD HEDT: Threadripper 7000 (5nm Zen 4) / 4-Channel DDR5 / 64 PCIe Gen 5 / 4096 SP6 Socket

But DDR5 should help somewhat with memory bandwidth.

 

[Exist50]

The point is that Intel didn't really "fix the problem". Their approach was twofold: mostly abandon HEDT after Skylake-X, and reduce throughput on remaining client parts with AVX512.

I included a link to a Hot Chips presentation on Ice Lake SP. To summarize, they eliminated the penalty on low-compute-intensity ops, and halved it for high intensity ones. This for a server chip. And if you actually want the throughput, then AMD's solution doesn't work either.

No reason for it not to clock as high as regular Ryzen on the first CCD, when only that one is utilized, IMO. When additional cores will be loaded, it can happily clock to 4,5GHz or 4 or whatever is needed to stay within the power limit.

There is one other possible consideration, current limitations. I'd assume the server socket dedicates fewer pins per CCX than AM5, so if an individual CCX was highly loaded, that might be the weak link limiting boost (out of the box).

I am not sure if AMD would like to go that route. There was an article by Puget System about memory channel performance. 8 Memory Channels gives trample 4 channels all day long.

The higher end config would obviously be far superior from a raw performance standpoint, but that's not the only consideration. The way I see it, there're a couple of different possibilities.

1. Market segmentation - Pretty simple. AMD doesn't want 8 channel HEDT SKUs competing with workstation/server ones.
2. Cost - AMD could be betting that the HEDT isn't willing to spend the kind of money they'd want for a Genoa-based config. The socket and motherboard alone would be very expensive.
3. Features - Since it's coming after Genoa, it's possible that AMD snuck in unique OC-oriented (required?) features into Siena.

 

[scineram]

I wonder if base Threadripper will return with 8 channels as based on Sienna, while Pro will be the full 12 channels from Genoa.

 

[DrMrLordX]

I included a link to a Hot Chips presentation on Ice Lake SP. To summarize, they eliminated the penalty on low-compute-intensity ops, and halved it for high intensity ones.

Given the state of their enterprise product stack, it seems like "too little, too late". AMD has chosen a different path. Once Dragon Range and Phoenix go live, AMD will have AVX512 compatibility top-to-bottom throughout their entire product stack. They may chase even higher SIMD throughput in the future, but that's questionable given that even IceLake-SP has to downclock a bit due to AVX512 instructions (which is a headache for some cloud providers).

 

[Exist50]

Given the state of their enterprise product stack, it seems like "too little, too late". AMD has chosen a different path. Once Dragon Range and Phoenix go live, AMD will have AVX512 compatibility top-to-bottom throughout their entire product stack. They may chase even higher SIMD throughput in the future, but that's questionable given that even IceLake-SP has to downclock a bit due to AVX512 instructions (which is a headache for some cloud providers).

"Too little, too late" for what? That implementation predates AMD's by ~2 years. And while I do agree that AMD having it across their lineup helps, if Intel doesn't do the same, that will hurt them just as much.

 

[DrMrLordX]

"Too little, too late" for what?

A significant amount of Intel's deployed enterprise silicon is still 2018's Cascade Lake-SP. IceLake-SP never got good traction, Sapphire Rapids is delayed until 2023, and Genoa is rolling along quite nicely. There are a few ES benchmarks showing Sapphire Rapids getting some (relatively) good AVX512 performance, but everywhere else, Genoa is going to dominate.

 

[Exist50]

A significant amount of Intel's deployed enterprise silicon is still 2018's Cascade Lake-SP. IceLake-SP never got good traction, Sapphire Rapids is delayed until 2023, and Genoa is rolling along quite nicely. There are a few ES benchmarks showing Sapphire Rapids getting some (relatively) good AVX512 performance, but everywhere else, Genoa is going to dominate.

Ok, sure. I thought you were talking about something AVX-specific.

 

[eek2121]

AMD will have AVX-512 from the top (servers) to possibly the bottom (laptops/embedded) unless they disable it on laptops for power savings. Intel should have added it to Gracemont while they were adding AVX.

Instead, Intel desktop and laptop chips have no support, and on the server it may or may not be present depending on if they lock it behind their feature unlock scheme.

Oh how the turn tables.

 

[nicalandia]

AMD will have AVX-512 from the top (servers) to possibly the bottom (laptops/embedded) unless they disable it on laptops for power savings.

Disabling it will only increase the power consumption as the FP unit needs to do twice the work... So Every Zen4 CPU from AMD from small two core embeded to Large Monster CPUs will have AVX-512 Enabled by default.

 

[LightningZ71]

AMD will have AVX-512 from the top (servers) to possibly the bottom (laptops/embedded) unless they disable it on laptops for power savings. Intel should have added it to Gracemont while they were adding AVX.

Instead, Intel desktop and laptop chips have no support, and on the server it may or may not be present depending on if they lock it behind their feature unlock scheme.

Oh how the turn tables.

The really sad part is that Intel could be selling a mobile workstation/desktop low end workstation part based on AlderLake 6+0 and 6+8/8+8 dies with the E cores fused off and AVX-512 enabled to cater to that market. Instead, we're left with whatever Tiger Lake-H and Rocket Lake products are still in the chain.

 

[nicalandia]

The really sad part is that Intel could be selling a mobile workstation/desktop low end workstation part based on AlderLake 6+0 and 6+8/8+8 dies with the E cores fused off and AVX-512 enabled to cater to that market. Instead, we're left with whatever Tiger Lake-H and Rocket Lake products are still in the chain.

They are just trying really hard to segment their features, The lowly ADL Celerons had AVX-512 on By default... Later they went to the trouble to just laser fuse them.

 

[DrMrLordX]

Ok, sure. I thought you were talking about something AVX-specific.

The point being that whatever improvements Intel has made to AVX clocks on their enterprise hardware are not well-represented in deployed silicon, and won't be for awhile. AMD's improvements (such as they are) will soon be ubiquitous, except for those holdouts that are still sitting on older hardware for whatever reason.

 

[Kaluan]

I saw someone in one of the Intel threads post some angry dude's twitter reply to HXL's (or whomever it was) post about the Phoronix article on impressive Zen4 AVX512 performance/efficiency... that Alder Lake is just as impressive, coming short of calling him a fanb...

First off, Alder Lake doesn't effectively have AVX512 at all (Alder Lake, not Sapphire). You have to go through 100 hurdles to activate it and when you do, you lose 1. Your E cores and 2. Any bug fixes and benefits the newer BIOS/microcode bring.

And secondly, it's simply not true:





Phoronix also did some testa, but only of very specific AVX512 CPU Mining (yuck), and even there power usage exploded w/ 8 core AVX512 and didn't bring any sort of power/performance benefit in half the sub-tests.

Sad that some still wanna die on that hill.

But hey, on the "upside" I can't wait to have my ears blown off by the constant "Zen4 doesn't have AMX!!1" now 😅

 

[nicalandia]

The first Ryzen 7600 Non-X posted on Geekbench CPU

Gigabyte Technology Co., Ltd. X670E AORUS MASTER - Geekbench

Benchmark results for a Gigabyte Technology Co., Ltd. X670E AORUS MASTER with an AMD Ryzen 5 7600 processor.

browser.geekbench.com

 

[Timmah!]

There is one other possible consideration, current limitations. I'd assume the server socket dedicates fewer pins per CCX than AM5, so if an individual CCX was highly loaded, that might be the weak link limiting boost (out of the box).

Thanks, did not consider that. However, if 1718 pins on AM5 socket is good enough for 5GHz+ 16C Ryzens, shouldnt 4096 pins on SP6 socket be good enough for 5GHz+ for 24/32C TR (obviously not on all cores)? Why would they dedicate fewer pins per CCX than AM5? Because of additional RAM channels or more I/O?

 

[nicalandia]

More Performance test on Genoa.

AMD Secure Memory Encryption "SME" Performance With 4th Gen EPYC Genoa Review - Phoronix

www.phoronix.com

 

[Exist50]

I saw someone in one of the Intel threads post some angry dude's twitter reply to HXL's (or whomever it was) post about the Phoronix article on impressive Zen4 AVX512 performance/efficiency... that Alder Lake is just as impressive, coming short of calling him a fanb...

First off, Alder Lake doesn't effectively have AVX512 at all (Alder Lake, not Sapphire). You have to go through 100 hurdles to activate it and when you do, you lose 1. Your E cores and 2. Any bug fixes and benefits the newer BIOS/microcode bring.

And secondly, it's simply not true:

View attachment 73198
View attachment 73199
View attachment 73200

Phoronix also did some testa, but only of very specific AVX512 CPU Mining (yuck), and even there power usage exploded w/ 8 core AVX512 and didn't bring any sort of power/performance benefit in half the sub-tests.

Sad that some still wanna die on that hill.

But hey, on the "upside" I can't wait to have my ears blown off by the constant "Zen4 doesn't have AMX!!1" now 😅

Uh, did you look at those graphs? Every single one of them shows an improvement for 8+0 AVX512 enabled vs disabled, including efficiency. Note that the top and bottom ones are higher=better, while the middle is lower=better.

And yeah, many things don't really benefit from the new ops AVX512 introduces, but they won't suffer a power penalty for it either, so it's a moot point. Where you see power explode is only where you're hammering through a ton of FLOPs, with performance to match.

 

[Exist50]

Thanks, did not consider that. However, if 1718 pins on AM5 socket is good enough for 5GHz+ 16C Ryzens, shouldnt 4096 pins on SP6 socket be good enough for 5GHz+ for 24/32C TR (obviously not on all cores)? Why would they dedicate fewer pins per CCX than AM5? Because of additional RAM channels or more I/O?

The IO, yes, but not just that. AM5 is designed to be able to pump 100W+ sustained through a CCX. Genoa seems to max out around 400W, which would be 1/3rd the power per CCX. It would be a complete waste (and increase costs a lot) to plumb in 3x the power capacity. Though yes, 12 DDR5 channels and 128 PCIe lanes will also take a ton of pins.

This is not my area of expertise, but the Gigabyte leak might have enough information to estimate whether this is actually an issue. These kind of details are key to the motherboard manufacturers.

 

[Asterox]

The first Ryzen 7600 Non-X posted on Geekbench CPU

View attachment 73203

Gigabyte Technology Co., Ltd. X670E AORUS MASTER - Geekbench

Benchmark results for a Gigabyte Technology Co., Ltd. X670E AORUS MASTER with an AMD Ryzen 5 7600 processor.

browser.geekbench.com

We could compare that with "10 core" i5 13400.

Geekbench Search - Geekbench

 

[nicalandia]

We could compare that with "10 core" i5 13400.

Geekbench Search - Geekbench

Gigabyte Technology Co., Ltd. X670E AORUS MASTER vs Z690 Steel Legend WiFi 6E - Geekbench

 

[nicalandia]

How about Ryzen 7600 vs Intel Raptor Lake 13900H?

Gigabyte Technology Co., Ltd. X670E AORUS MASTER vs SAMSUNG ELECTRONICS CO., LTD. 960XFH - Geekbench

 

[Kaluan]

Uh, did you look at those graphs? Every single one of them shows an improvement for 8+0 AVX512 enabled vs disabled, including efficiency. Note that the top and bottom ones are higher=better, while the middle is lower=better.

And yeah, many things don't really benefit from the new ops AVX512 introduces, but they won't suffer a power penalty for it either, so it's a moot point. Where you see power explode is only where you're hammering through a ton of FLOPs, with performance to match.

...nice gargantuan straw man there buddy.

IDK how to tell you but if using E cores nets you more performance and/or efficiency... then I don't see the point in using AVX512 and crippling your CPU's general performance.

And what's this spin I see you making about increased power efficiency, fact is Zen4 performance goes up and power consumption stays the same or even goes down. Alder Lake's power doesn't go down, it doesn't even stay the same. So what exactly are you arguing? That AVX512 is great for just SOME things? Well shucks, I didn't know that! lmao

 

[Exist50]

IDK how to tell you but if using E cores nets you more performance and/or efficiency... then I don't see the point in using AVX512 and crippling your CPU's general performance.

The entire argument I was responding to was that AVX512 "cripples" Intel's CPU performance/efficiency via a frequency and power penalty. Nothing to do with hybrid at all. Reread the past few comments if you've missed them.

And yes, it is an absurd claim.

 

[Kaluan]

The entire argument I was responding to was that AVX512 "cripples" Intel's CPU performance/efficiency via a frequency and power penalty. Nothing to do with hybrid at all. Reread the past few comments if you've missed them.

And yes, it is an absurd claim.

Well, i was arguing within a different context, that in which some made the specious argument that somehow Alder Lake (ADL, not Golden Cove) is also great at AVX512 yet no one lauded it like Zen4. Nevermind then.

 

[biostud]

I was was wondering about the pricing of the motherboards, and if the rumors are true that it is the high requirements for power delivery that makes the boards more expensive than previous generations. Should AMD make a "B630" that had same features as the B650, but did not support the most power demanding CPUs, so that the entry level for AM5 could be lower or do you think the A series will be enough, when they are launched?