You forgot situation 3: For some reason Zen 5's IPC increase (whatever it may be) is extremely variable by workload so people never stop arguing how much IPC increase there really wasI see two potential futures for the AMD Hype Train when AMD does eventually reveal Zen 5.
Situation 1: IPC increase is <20%. The Hype Train crashes spectacularly.
Situation 2: IPC increase is >40%. The Hype Train takes off, enters low earth orbit and goes to Heaven.
I vote this should be the new "Solution" to this thread.Until a new Zen 6 thread comes, then leakers come out of grinding in the woods fully levelled up in the RPG games starting in level 0.
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I don't because there is a possibility(who knows how big, tho) that this will age like milk.I vote this should be the new "Solution" to this thread.
Nestbrust introduced today's key solutions that are also used by AMD. Netbrust was a necessary lesson for Intel, whose solutions were used in subsequent generations.
A 1-way x86 decoder will not provide IPC level 3, let alone 4 or 6 instructions per cycle.
Well, I don't intent the "Solution" post to be a "real" solution, just the funniest post in the thread lolI don't because there is a possibility(who knows how big, tho) that this will age like milk.
I know that I was sceptical, about Zen 5 rumors, but being too sceptical is also not a good thing.
We have to keep open mind to EVERY possibility.
Why do I see Polish language here?Tylko dośiadczenie z bezpośrednimi następcami Pentium III czyli Banias, Dothan i Yonah pozwoliły Intelowi opracować Conroe.
It's likely a balance between a larger mop cache and wider decode. Increasing the IPC in modern CPU architectures is all about eking out gains in corner cases, so if the corner cases are when you're decode limited, then that's where resources should be poured.You know that modern cpus have 0-way x86 decoder when they extract their max IPC throughput? Decoders are shut off completely and even power-gated when executing tight loops. Wide decoders are mostly needed when IPC levels are way under that magic 1-level like after context switches.
Well, I don't intent the "Solution" post to be a "real" solution, just the funniest post in the thread lol
All right. Now show me a high IPC core with only a one-way instruction decoder.You know that modern cpus have 0-way x86 decoder when they extract their max IPC throughput? Decoders are shut off completely and even power-gated when executing tight loops. Wide decoders are mostly needed when IPC levels are way under that magic 1-level like after context switches.
The Zen 4 letdown is based on the IPC jump expectations set by the Zen 2->3 transition - 19% IPC on the same process, TDP kept, launched just 16 months apart. Keep in mind the 25% IPC figure was floating around until the Gigabyte leak.The number of people who took that and declared Zen 4 a failure was quite astounding, then the part launched and it was quite a bit better than even AMD were indicating.
no?The Zen 4 letdown is based on the IPC jump expectations set by the Zen 2->3 transition - 19% IPC on the same process, TDP kept, launched just 16 months apart.
Speaking from someone who had a fleet (6) 5950x's and 8 7950x's, I can say thats it more than clock freq. Just avx-512 alone in many scientific apps is like 20-30% improvement.The "letdown" was that the improvement was in clock speed rather than IPC like the hype train said. They simply did as Intel did and it was disappointing to those who expect AMD to be better.
Zen 4 is highly power efficient, even though it is clocked very high. Not sure what it is exactly what AMD supposedly has been doing as Intel did.The "letdown" was that the improvement was in clock speed rather than IPC like the hype train said. They simply did as Intel did and it was disappointing to those who expect AMD to be better.
Absolutely.Considering that if Zen 4 was a pure tick, the clock speed gains are pretty decent (~25%). It's not common you get that big of a leap in clocks from a tick alone in modern times. Honestly, if there were no IPC gains, 25% higher performance isn't a bad uplift for a new generation at all, but then you tag on another 11-13% IPC gain too and it's the cherry on top of the ice cream sundae.
Currently we are at the stage of front running the disappointment that Strix Point is.So now the rumor is -5% IPC? Mmmm, bulldozer 2.0 … yummy
Zen1 is an average IPC of +52% higher than Excavator, but it barely reached the level of Haswell from 2014.
What are you talking about, it was above Broadwell, let alone Haswell, you should look at hold reviews rather than relying on random internet urban legends.
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If you look at this overall performance comparison from the Anandtech review, the 1800X is ~3% faster overall than a 5960x and around 6% slower than a 6900K. (The gradients appear to represent 6.66%)
Getting detailed frequency info seems to be a challenge, but the 1800X spec is 3.6 base/4.0 boost while the 5960X spec is 3.0 base/3.5 boost.
I think you may have followed it up in a subsequent post, but IIRC Conroe was a revamp of the PIII mobile architecture, Netburst burst it's own bubble, see Prescott. Last good Netburst was Northwood, or P4c IIRC.But Netbrust was a high-clock microarchitecture with a 1-way x86 decoder.
Today, GoldenCove has a 6-way decoder that is wider than previous generations, unlike Netbrust whose decoder was narrower. The Pentium III had a 3-way decoder.
So the massive growth of IPC Conroe was no miracle compared to Netbrust. Compared to IPC Yonah, it was simply the generational leap that could be expected from the next generation. Additionally, the effect was intensified by the slightly exaggerated drama that Intel would no longer be able to develop a new architecture with a higher IPC than the K8.