We know pretty much nothing, at this point. Mostly 20-odd pages of speculation, with the occasional vague quote or slide from AMD.Not to be that one guy, but can I get a summary of the last 27 pages?
RDNA3+ in GNR? Are you sure about that?Not very likely I think, diminishing returns for DT especially with faster DDR5.
I also would like to see a 12 core CCD on N4P. But...the CCD is going to be large.
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Totally guessing based on Mike's statement's
12C per L3
L2 1MiB --> 1.5MiB
L3 4MiB/Slice --> 3MiB/Slice = 36MiB/CCD
GMI SerDes PHY replaced with a lower power PHY with small beach head.
A ring with quadrants would probably be suitable to cut latency across 12 cores. Additionally the faster interconnect should help when snooping the other CCX.
Even with this, CCD seems a bit too big for AMD, ~100mm2 is quite big. Unless, they manage to use the perf gains from N4P and claw back some density tradeoffs to reach at least ~90mm2.
On the other hand N4/5 supply is plenty in 2024, 180k+ wpm.
Additionally, the IOD will be totally new. RDNA3+ and AIE for DT as well.
Too much unknowns but interesting for me to ponder about this, as usual.
Everything on this thread is unsure until next year my friend, that is why I am not dropping assertive sentences and not being smug at all.RDNA3+ in GNR? Are you sure about that?
Too much unknowns but interesting for me to ponder about this, as usual.
Any idea why both AMD and Intel are using the word granite for their future CPUs? Does it mean that both are confident that their bets are gonna be SOLID? Or the process of making them was volcanic?
Still silicon when you know your geology! 😂They switching from Silicon to Granite based logic ... 🤭
what you're saying is there exists a venn diagram of men understanding women and computer geeks figuring out the next gen processor.We know pretty much nothing, at this point. Mostly 20-odd pages of speculation, with the occasional vague quote or slide from AMD.
Going by Raphael having RDNA2 in its IOD it doesn't seem like a huge stretch.RDNA3+ in GNR? Are you sure about that?
It would make sense to do so and I was only suggesting it mostly from ease of software maintainability not for performance per se, because in 2024 RDNA2 would be 4 years old.Going by Raphael having RDNA2 in its IOD it doesn't seem like a huge stretch.
ExecuFix mentioned max cTDP of Turin at 50% more than Genoa.
I suppose we could guess a similar increase in core count assuming they didn't regress in per core TDP on a newer node. Between 128 and 144 Cores . (33% - 50% more cores)
400W max cTDP/4.2W per core for Genoa(9564), 280W max cTDP/4.4W per core for Milan(7763)/Rome(7H12), ignoring IOD for this math
| Raphael | Genoa | Bergamo | Turin | Bergamo 5c | |
| CPU Architecture | Zen 4 | Zen 4 | Zen 4c | Zen 5 | Zen 5c |
| TSMC - Power Efficiency | N5 | N5 | N5 | N3E - 34% | N3E - 34% |
| Cores Per Chiplet | 8 | 8 | 16 | 8 | 16 |
| Max CCD | 2 | 12 | 8 | 16 | 12 |
| L3 Cache Per Chiplet | 32MB | 32MB | 32MB | 32MB | 32MB |
| Max L3 Caches | 64MB | 384MB | 256MB | 512MB | 384MB |
| TDP | 65W | 360W | 360W | 600W | 600W |
| - IOD power (120W) | 240W | 240W | 480W | 480W | |
| Power per chiplet | 30W | 20W | 30W | 30W | 40W |
| Power per Core | 3.75W | 2.5W | 1.88W | 3.75W | 3.33W |
These calculations are a bit scuffed cuz the IO die isn't a part of the calculations, as far as I see hereI have been thinking about max TDP for a while, but I would like to calculate how much power per chiplet to have clearer picture. Both Genoa and Bergamo chiplets have max default TDP of 360W, let's assume Turin and Bergamo 5c with max cores as rumored (that would be 192 Zen 5 cores and 256 Zen 5c cores) have max TDP of 600W per socket. Below is my calculation:
Raphael Genoa Bergamo Turin Bergamo 5c CPU Architecture Zen 4 Zen 4 Zen 4c Zen 5 Zen 5c TSMC - Power Efficiency N5 N5 N5 N4P - 22% N3E - 34% Cores Per Chiplet 8 8 16 16 32 Max CCD 2 12 8 12 8 L3 Cache Per Chiplet 32MB 32MB 32MB 64MB 64MB Max L3 Caches 64MB 384MB 256MB 768MB 512MB TDP 65W 360W 360W 600W 600W Power per chiplet 30W 30W 45W 50W 75W Power per Core 3.75W 3.75W 2.81W 3.13W 2.34W
- Both Bergamo and Bergamo 5c could only have 8 chiplets per socket cause they are having bigger die size due to double core counts. OTOH, their L3 caches would be smaller than Genoa/Turin, you can't have both more core counts and bigger L3 cache at the same time.
- With power efficiency improvements, I believe Turin would fit in double core counts with same socket. I also expecting some clock regression and higher IPC from Zen 5 architecture. What do you think?
For simple round figures, I omit the IOD's power. And with 8-12 chiplets per socket, the IOD's power figure is negligible. You could deduct around 2 watts per chiplet if you want. What I am interested is does the power increase warrants doubling core counts in upcoming Zen 5/5c chiplet?These calculations are a bit scuffed cuz the IO die isn't a part of the calculations, as far as I see here
The rumors say? 🙂 This is all out in the open with extreme detail for months..
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From Genoa thermal design guide, Max IOD power is 120W around. Which gives about 2.91W/Core Max.I have been thinking about max TDP for a while, but I would like to calculate how much power per chiplet to have clearer picture. Both Genoa and Bergamo chiplets have max default TDP of 360W, let's assume Turin and Bergamo 5c with max cores as rumored (that would be 192 Zen 5 cores and 256 Zen 5c cores) have max TDP of 600W per socket. Below is my calculation:
Raphael Genoa Bergamo Turin Bergamo 5c CPU Architecture Zen 4 Zen 4 Zen 4c Zen 5 Zen 5c TSMC - Power Efficiency N5 N5 N5 N4P - 22% N3E - 34% Cores Per Chiplet 8 8 16 16 32 Max CCD 2 12 8 12 8 L3 Cache Per Chiplet 32MB 32MB 32MB 64MB 64MB Max L3 Caches 64MB 384MB 256MB 768MB 512MB TDP 65W 360W 360W 600W 600W Power per chiplet 30W 30W 45W 50W 75W Power per Core 3.75W 3.75W 2.81W 3.13W 2.34W
- Both Bergamo and Bergamo 5c could only have 8 chiplets per socket cause they are having bigger die size due to double core counts. OTOH, their L3 caches would be smaller than Genoa/Turin, you can't have both more core counts and bigger L3 cache at the same time.
- With power efficiency improvements, I believe Turin would fit in double core counts with same socket. I also expecting some clock regression and higher IPC from Zen 5 architecture. What do you think?
I'd say yes. Because of the nature of the V/f curve, half the power per core nets you quite a lot more than half the performance. With the right architecture, you basically get the more, the lower you go.For simple round figures, I omit the IOD's power. And with 8-12 chiplets per socket, the IOD's power figure is negligible. You could deduct around 2 watts per chiplet if you want. What I am interested is does the power increase warrants doubling core counts in upcoming Zen 5/5c chiplet?
I believe AMD's recent architectures scale even better than Intel's in that regard as well. They don't continue scaling as well into higher power levels as Intel, but they have way better scaling at the low power levels.I'd say yes. Because of the nature of the V/f curve, half the power per core nets you quite a lot more than half the performance. With the right architecture, you basically get the more, the lower you go.
I just find a 16 core Zen 5 chiplet extremely hard to swallow.Thanks for the IOD's TDP numbers, I am surprised by the 120W figures, guess 12-channel DDR5 support needs more power. I have updated the table with TDP after deducting IOD's power. Guess what, the new numbers are essentially double. That's mean even with double core counts, each core still getting same amount of power..... And I am more confident with AMD's planning of Turin family and to some extent, Granite Ridge...
AMD could potentially double the cores for upcoming desktop CPU, with total TDP of around 90W (40W + 40W + 10W for IOD). As for successor of Dragon Range, AMD could just use one chiplet to serve 16-core Zen 5 with TDP of 50W.
We have had 8 core chiplets for a while now, the core count increase is in order. 12 is also a nice number.I just find a 16 core Zen 5 chiplet extremely hard to swallow. ... That's a >60% increase in the size of each CCD. I don't think AMD do that.
I am thinking more in the line of 8c Zen5 CCD + VCache and 16c CCD, 2*8 CCX Zen5c or Zen4c.I just find a 16 core Zen 5 chiplet extremely hard to swallow.
The core size increase from Zen 2 to Zen 3 was ~35%, and the core logic itself (without L2 and L3) was a ~40% increase.
Zen 3 was also a "grounds up architecture" much like Zen 5 is looking to be.
Now let's imagine Zen 5.
Let's assume Zen 5 scales similar to Zen 3.
Zen 4's 3.69 mm^2 x 1.3 = 4.80, x 0.95 because of 4nm, 4.56 mm^2 per core.
4.56 x 16 = 72.96 mm^2 for the cores alone. This isn't counting stuff like power banks on the core, or even the L3 for example. Essentially, just the cores and L2 of 16 zen 5 cores are the same size as the entire zen4 CCD. The L3 on zen 4 is an additional 25mm^2 too. All things considered, a 16 core zen 5 CCD would be ~115mm^2 imo. That's a >60% increase in the size of each CCD. I don't think AMD do that.
On 3nm, it looks a lot better, but I don't think 3nm on zen 5 is going to be standard anyway except maybe for Zen 5C or servers.
¯\_(ツ)_/¯I am thinking more in the line of 8c Zen5 CCD + VCache and 16c CCD, 2*8 CCX Zen5c or Zen4c.