Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Arrow Lake Refresh (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXDesktop OnlyMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2025 ?Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E8P + 32E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ??8 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15



Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

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SiliconFly

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Mar 10, 2023
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I don't think we'll see any serious delays anymore... ...it's all about the people working on it.
More than the people, it's the process. It was one of Jim Keller's primary tasks. Now that MTL is out and the process is in place, future processors shouldn't experience any more serious delays as dependencies are minimal and each team works individually and faster. They save a ton of time in debugging and validation. One of the main reason they're able to work on both ARL & LNL at the same time.
 

eek2121

Platinum Member
Aug 2, 2005
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It does if yields are too low on Intel 4 to produce a monolithic die of that size. Admittedly it makes more sense for a High NA EUV process with smaller reticle limits.
Intel’s yields on Intel 4 are said to be higher then Intel 7.
View attachment 91607
LNL gets shown off. Compute die, SOC die, and rumored dummy structural die.
Area efficiency doesn't look too great TBH. The compute die alone on N3 looks to be the same size as the M3 die.
Big cores + it combines GPU + CPU.
LNL is N3B

Side note: Intel doesn't have any N3E products in 2024.

*sigh* here we go again.

The package Intel showed off? The compute did was apparently made on Intel 18a (they also showed off a wafer full of them). Intel’s last public slide mentioning lunar lake also showed 18A.

I have only found 1 single original source for the N3B rumors, and he cites “unnamed sources” which is code for “I might be making this up.”

Intel would look pretty foolish talking about process leadership and coming up with this elaborate plan, executing on it for years, and then turning around and saying “just kidding guys, IFS sucks, we are using TSMC”.

You would sooner convince me that AMD is using IFS.
 
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trivik12

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Jan 26, 2006
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We should get benchmark leaks in next few months if the systems are with OEM. There is no way intel can keep it under wraps. If course these early samples will not be at similar clockspeeds to retail but hopefully ipc numbers can be judged. If oneraichu is correct, LNC will be 8-wide core. So that would be close to Apple cores(which are 9-wide if I am not wrong). Question is would Intel would bump up cache numbers. Plus the most important thing is performance per watt. I dont think current chips lack in performance.

I dont think Lunar Lake can release this year if it uses 18A. That will go to volume production only late this year. It cannot release until mid next year. It could be 20A or N3.
 
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Hitman928

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Apr 15, 2012
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Intel’s yields on Intel 4 are said to be higher then Intel 7.

Big cores + it combines GPU + CPU.


*sigh* here we go again.

The package Intel showed off? The compute did was apparently made on Intel 18a (they also showed off a wafer full of them). Intel’s last public slide mentioning lunar lake also showed 18A.

I have only found 1 single original source for the N3B rumors, and he cites “unnamed sources” which is code for “I might be making this up.”

Intel would look pretty foolish talking about process leadership and coming up with this elaborate plan, executing on it for years, and then turning around and saying “just kidding guys, IFS sucks, we are using TSMC”.

You would sooner convince me that AMD is using IFS.

Looks pretty legit to me? I think the current leaks point to the first and bulk of LNL being on N3B with a smaller volume being on 18a next year.

 
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SiliconFly

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Mar 10, 2023
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Intel’s yields on Intel 4 are said to be higher then Intel 7.
Intel 4 may have higher yields than Intel 7. But Intel 7 is a high volume node. Tons of capacity. Intel 4 not so much cos it's a purpose built node for MTL's CPU tile.

*sigh* here we go again.

The package Intel showed off? The compute did was apparently made on Intel 18a (they also showed off a wafer full of them). Intel’s last public slide mentioning lunar lake also showed 18A.

I have only found 1 single original source for the N3B rumors, and he cites “unnamed sources” which is code for “I might be making this up.”

Intel would look pretty foolish talking about process leadership and coming up with this elaborate plan, executing on it for years, and then turning around and saying “just kidding guys, IFS sucks, we are using TSMC”.

You would sooner convince me that AMD is using IFS.
Maybe he was making it up. Even I has a hard time believing Intel will shift their CPU tile to TSMC. Feels wrong.

But after looking at this photo, it isn't clear anymore. LNL has a single CPU+GPU tile. Does that mean LNC+Battlemage are on a Intel node now? Or is it the other way around that both LNC+Battlemage are on TSMC? I thought Battlemage was a TSMC only design considering the upcoming Battlemage dGPU card is N3B. It's super expensive for amd, nvidia & also for Intel to have 2 different designs for the same gpu on 2 different nodes at the same time. I don't think it's even viable.

Also, 18A is at least 6 months behind 20A according to Intel themselves. Meaning, early 2025 volume ramp & time to market will be Q3 2025 at best. LNL is a Q4 2024 product. The timelines don't add up. LNL can't be on 18A. LNL on N3B makes sense (as Battlemage dGPU is N3B & LNC is node agnostic). LNL on 20A also makes some sense as LNC is already on 20A (due to ARL). But LNL on 18A, nah.
 
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DavidC1

Senior member
Dec 29, 2023
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Lunarlake is TSMC N3B. I don't know why that's such a hard thing to believe. Intel 4 and 20A doesn't have full libraries for Lunarlake either. It also was in concept during a time when the confidence towards their process was very low.

Also, Meteorlake's battery life is so great Lenovo has introduced a laptop where the base portion is Meteorlake and Tablet portion is Snapdragon.
 
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DavidC1

Senior member
Dec 29, 2023
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Looks at SPR
This is what I meant when I said for short cycle products like semiconductors delays make it worse. It's what 3 years late now?

Surely you can't think current SPR is such an improvement over maybe original DMR plans?

@Hitman928 Feast on this glory.
 

DavidC1

Senior member
Dec 29, 2023
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Can't be very sure. All evidence points to N3B... but we still need some form of official confirmation before it becomes a fact. Cos, CPU tile on TSMC is a big deal for Intel imho (I maybe wrong).
It is a big deal. They had to cause they screwed up. If it was on their own process they would have said it. You don't need them to be confirming to know what's going on. You can read between the lines so to speak, unless you are ChatGPT.
 

Hitman928

Diamond Member
Apr 15, 2012
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LNL is N3b.
It's also very huge for what it is.

Any idea why it's so big? Based on the leaked block diagram, it looks like the P-cores have L3 and then there is an additional 8mb of SLC which will take up some space but even still, it seems a bit big for a 4P+4E compute core. Are the iGPU and/or NPU taking up a ton of space?
 

DavidC1

Senior member
Dec 29, 2023
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All those who believe Lunarlake is Intel process are probably the same that still believe Kraznich got fired over sleeping with a subordinate, when Intel was hosting "private" parties for executives and systems partners after Intel Developer Forum was over.

Suure. Whatever makes you sleep at night.
 

adroc_thurston

Platinum Member
Jul 2, 2023
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but we still need some form of official confirmation
Slides posted are the official confirmation.
Any idea why it's so big? Based on the leaked block diagram, it looks like the P-cores have L3 and then there is an additional 8mb of SLC which will take up some space but even still, it seems a bit big for a 4P+4E compute core. Are the iGPU and/or NPU taking up a ton of space?
Well let's just say LNC is huge and bad.
 

cebri1

Member
Jun 13, 2019
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Lunarlake is TSMC N3B. I don't know why that's such a hard thing to believe. Intel 4 and 20A doesn't have full libraries for Lunarlake either. It also was in concept during a time when the confidence towards their process was very low.

Also, Meteorlake's battery life is so great Lenovo has introduced a laptop where the base portion is Meteorlake and Tablet portion is Snapdragon.

Actually is pretty good in most reviews but it's not a tablet chip.

 

dullard

Elite Member
May 21, 2001
25,126
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Intel would look pretty foolish talking about process leadership and coming up with this elaborate plan, executing on it for years, and then turning around and saying “just kidding guys, IFS sucks, we are using TSMC”.

You would sooner convince me that AMD is using IFS.
Is this the hill you are going to fight for? Evidence for your side: you think that is the way it would be. Heck, your own argument fails on its own merits (TSMC already is producing some E cores on Meteor Lake).

Evidence that Intel will use TSMC:
1) From Intel:
https://www.intel.com/content/www/u...technology-roadmaps-milestones.html#gs.2tquli
Lunar Lake and Beyond – Fueled by its IDM 2.0 strategy, Intel will be using both internal and external process nodes to deliver leadership products.

2) From Intel: https://download.intel.com/newsroom/2022/corporate/2022-Intel-Investor-Meeting-Client.pdf

Combine that with a 2024 Lunar Lake launch and 18A not launching until 2025 makes a pretty strong case for External.

3) Supposedly leaked from Intel: https://www.tomshardware.com/news/intel-lunar-lake-mx-to-use-tsmc-n3b


4) From Intel (Gelsinger): https://www.anandtech.com/show/1657...-on-intel-ip-blocks-for-foundry-cores-on-tsmc
Intel’s x86 Designs No Longer Limited to Intel on Intel: IP Blocks for Foundry, Cores on TSMC

5) From Intel (Gelsinger): https://www.tomshardware.com/news/intel-pat-gelsinger-clients-want-custom-x86-socs
We are going to make selective use of foundries. […] If I need to use a foundry to have a unique product or a halo product and certain portions, absolutely.

I could go on, but they are just variations of the above.
 
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Geddagod

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Dec 28, 2021
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This is what I meant when I said for short cycle products like semiconductors delays make it worse. It's what 3 years late now?
I think it's 5? years late. Development started 2015 IIRC, if they expected development to take 3 years, that would be released in 2018, and SPR launched 2023.
Surely you can't think current SPR is such an improvement over maybe original DMR plans?
Idk what you mean by this, I'm sorry
 

Geddagod

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Dec 28, 2021
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The compute did was apparently made on Intel 18a (they also showed off a wafer full of them). Intel’s last public slide mentioning lunar lake also showed 18A.
Cap. Source?
Intel would look pretty foolish talking about process leadership and coming up with this elaborate plan, executing on it for years, and then turning around and saying “just kidding guys, IFS sucks, we are using TSMC”.
ARL is dual sourced. It uses 20A as well.
And server chips, aka the big "wow you can yield!" chips are on Intel nodes as well.
with a smaller volume being on 18a next year.
I don't think LNL will ever be on 18A, unless it's a LNL successor, but isn't that just PTL as well?
Intel 4 and 20A doesn't have full libraries for Lunarlake either.
Intel doesn't like fin depopulation. Undense, large cores with UHP and HP logic cells are their mojo. Last time they tried to buck that trend, it exploded in their faces.
Well let's just say LNC is huge and bad.
The LNC core complex looks to be around as big as a RWC core complex. I doubt a Zen 5 core complex is any smaller, unless they managed to get a really good shrink on the ringbus and L3 portions of the core complex, and even then...
Not at all. No one knows how performant LNC is gonna be. It can be a dud... or it might be out of the world.
With all the info so far, it looks bad. The only person saying its good is MLID.
Also idk why you have such a hard time believing this, but whatever.
 

adroc_thurston

Platinum Member
Jul 2, 2023
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No one knows how performant LNC is gonna be
ARL numbers are known lol.
The LNC core complex looks to be around as big as a RWC core complex.
Yeah on N3. That's the problem.
I doubt a Zen 5 core complex is any smaller, unless they managed to get a really good shrink on the ringbus and L3 portions of the core complex, and even then...
Z5 quad is considerably higher performance, while being N4p.
With all the info so far, it looks bad
At least Skymont is decent so there's that.
 
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