Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

jpiniero · Apr 12, 2024

jur said:
I wonder what's preventing Intel from expanding their capacity.

Intel needs their 90% server market share back.

SiliconFly · Apr 12, 2024

Ghostsonplanets said:
first instead of following Intel propaganda

Looks like you're following AMD propaganda in an Intel thread.

Ghostsonplanets said:
Or perhaps i18A doesn't bring "unquestioned leadership".

Read it. Interesting. Since you're so confident, what makes you think TSMC N2 differs a lot from Intel's "lithographic patterning of 30-36 nm pitch metal layers of Intel 18A technology node"?

Ghostsonplanets said:
Anyway, I'm dropping this.

Your choice. But I too think you should. Cos it's starting to sound silly.

N2 & 18A share similar PPA & hence similar transistor characteristics like half-pitch, gate length, etc, frequency, efficiency & performance too (at least for a given library). In your own words, you may think think 18A is inferior or more like Intel 4 or like TSMC 5nm. But reality is far different.

SiliconFly · Apr 12, 2024

jur said:
I wonder what's preventing Intel from expanding their capacity. Is there some other bottleneck besides EUV tools? They ordered 6 high NA tools and each of these costs twice as much as latest low NA tool. This seems very irrational decision. Wouldn't it make much more sense to ramp 18A as fast as possible, especially if the process is really as good as they say. Besides, they have Synopsis, Cadence helping them with automation tool, libraries,.. and apparently also customers, not to mention internal designs that are being sent to TSMC...

Lack of EUV was a major hurdle initially. And still a hurdle. For example, out of the 6 High-NA, only one is installed and is still not fully functional yet. And it's expected to go into production only in 2026-27 timeframe.

Lithos in general (DUV, EUV & High-NA) take hell a lot of time to go online. For all the EUV orders Intel placed a couple of years back, we're starting to see some results only now. They will get there eventually.

Aapje · Apr 12, 2024

Ghostsonplanets said:
Yes, we're supposed to believe Intel will have capacity and manufacturing volume to do a vast amount of SKUs in the next 1- 2 years. But suddenly they'll lack it for NVL🤔.

Or perhaps i18A doesn't bring "unquestioned leadership".

AFAIK they never claimed that they would ship most, but just that their process would be the best...eventually.

@jur

Keep in mind that ASML isn't exactly a supermarket where you go in and the machines are lined up on the shelf for you to take home.

Even installing and dialing in these machines is a very lengthy process.

dullard · Apr 12, 2024

jur said:
I wonder what's preventing Intel from expanding their capacity. Is there some other bottleneck besides EUV tools? They ordered 6 high NA tools and each of these costs twice as much as latest low NA tool. This seems very irrational decision. Wouldn't it make much more sense to ramp 18A as fast as possible,

1) There is one and only one EUV supplier, with a massive backlog of orders. https://www.tomshardware.com/news/a...-hits-record-backlog-exceeds-dollar38-billion
2) There has been a massive chip demand boom. Covid shortages, crypto, and now AI. This makes the backlog for equipment even larger.
3) Intel didn't buy enough EUV machines and then didn't get in line for the machines early enough. Intel had bad management that made bad decisions. They totally missed the ball for this chip demand boom.

Combine the three and Intel is bottlenecked. There is no possible way to ramp 18A much faster without the equipment to do so.

Hulk · Apr 12, 2024

Intel with 18A in one hand behind their back and Intel 7 in the other hand saying, "Don't look at that look at THIS!"

jpiniero · Apr 12, 2024

dullard said:
2) There has been a massive chip demand boom. Covid shortages, crypto, and now AI. This makes the backlog for equipment even larger.

Not really, not anymore. The AI stuff is all packaging limited. Even N5, TSMC is in the process of retooling some of it for N3 and friends.

Intel doesn't have much capacity because they were hedging on whether to spin off the fabs... and whether they can actually afford to continue without putting the company at risk.

H433x0n · Apr 12, 2024

SiliconFly said:
Read it. Interesting. Since you're so confident, what makes you think TSMC N2 differs a lot from Intel's "lithographic patterning of 30-36 nm pitch metal layers of Intel 18A technology node"?

Where do you get 30-36nm pitches? And what feature?

Hans Gruber · Apr 12, 2024

jpiniero said:
Not really, not anymore. The AI stuff is all packaging limited. Even N5, TSMC is in the process of retooling some of it for N3 and friends.

Intel doesn't have much capacity because they were hedging on whether to spin off the fabs... and whether they can actually afford to continue without putting the company at risk.

The technology bill passed by Biden provides tens of billions to Intel and other companies to build and expand their fabs. Even TSMC got several billion for their Arizona operations.

Hulk · Apr 12, 2024

Hans Gruber said:
The technology bill passed by Biden provides tens of billions to Intel and other companies to build and expand their fabs. Even TSMC got several billion for their Arizona operations.

Hey, it's just money. Print away.

poke01 · Apr 12, 2024

Thoughts on skymont?

FlameTail · Apr 13, 2024

poke01 said:
Thoughts on skymont?

DrMrLordX · Apr 13, 2024

jur said:
They ordered 6 high NA tools and each of these costs twice as much as latest low NA tool.

To add to what others have said, keep in mind that Intel has abandoned plans to make 20a and/or 18a High NA EUV processes. The acquisition of advanced equipment has no bearing on their processes through the entirety of 2025.

Doug S · Apr 13, 2024

H433x0n said:
Where do you get 30-36nm pitches? And what feature?

Pitches have been misleading for a long time and are becoming even more misleading. Intel is increasing its pitch from 30 to 36nm with 18A because BSPDN/PowerVia allows a larger M0 pitch without compromising density which helps in multiple ways.

H433x0n · Apr 13, 2024

Doug S said:
Pitches have been misleading for a long time and are becoming even more misleading. Intel is increasing its pitch from 30 to 36nm with 18A because BSPDN/PowerVia allows a larger M0 pitch without compromising density which helps in multiple ways.

What's the source for that? As far as I know there's nothing public on the features of 18A.

SiliconFly · Apr 13, 2024

H433x0n said:
Where do you get 30-36nm pitches? And what feature?

Ghostsonplanets posted a link recently. It sheds some light, but not the whole picture. Even I remember reading a while back that they were able to increase (i think) the gate pitch since they managed to move the PDN to the other side for better performance and lower IR droop or something. Not sure about the details though. When N2 comes out with BSPD, we should be able to expect something similar.

Aapje · Apr 13, 2024

H433x0n said:
What's the source for that? As far as I know there's nothing public on the features of 18A.

Intel put out a slide:

Intel Details PowerVia Chipmaking Tech: Backside Power Performing Well, On Schedule For 2024

www.anandtech.com

Ghostsonplanets · Apr 13, 2024

poke01 said:
Thoughts on skymont?

Should be a really good core. Kepler recently said that SKT has around SNC/Z3 performance. So you're basically getting an extra 5950X, alongside 8 Lion Cores, if you buy Core Ultra 9 2990K.

Should help ARL be a MT monster. On LNL, it will act more as a LPE core because it will lack L3 cache and is "off-ring" (iirc).

tamz_msc · Apr 13, 2024

Ghostsonplanets said:
SKT has around SNC/Z3 performance

Gracemont in Alder Lake already is ~95% of the per-clock integer performance of Cypress Cove. In Raptor Lake, it should surpass the PPC of Cypress Cove. Skymont should at minimum be Golden Cove level of PPC.

All this is based on the SPECint_rate 2017 1T numbers from past Anandtech reviews.

mikk · Apr 13, 2024

It's not clear if they refer to performance from IPC and clock speed combined. If it's IPC then I would agree SNC level isn't great when Gracemont already was basically on par with Skylake, at least on integer workloads. And seems like the Skymont cluster in Lunar Lake is quite a bit bigger now compared to Lion Cove big core.

https://twitter.com/x/status/1778860445853491346

SolidQ · Apr 13, 2024

Some news

https://twitter.com/x/status/1779161220807045335

tamz_msc · Apr 13, 2024

SolidQ said:
Some news

https://twitter.com/x/status/1779161220807045335

iTLB entries are the exact same as Golden Cove.
2M/4M doesn't refer to L2/L3 size.

H433x0n · Apr 13, 2024

Aapje said:
Intel put out a slide:

Intel Details PowerVia Chipmaking Tech: Backside Power Performing Well, On Schedule For 2024

www.anandtech.com

That’s for Intel 4, not 18A.

Thibsie · Apr 13, 2024

Ghostsonplanets said:
It's fake. Huge Intel fanboy that doesn't know anything and he's usually all the time around tech twitter trying to get leaks.

Anyway, you can spot on that it's fake due to him claiming CPU tile and SoC tile are separated tiles fabricated on different nodes. While, from what we know, CPU and SoC tile are merged on PTL. The CPU core configuration is also straight out of MLID videos.

Yeah, that guy isn't worth the attention.

mikk · Apr 13, 2024

Thibsie said:
Yeah, that guy isn't worth the attention.

Too bad Ghostsonplanets is wrong with his tile prediction. Just because LNL integrate Soc into the compute tile doesn't mean Intel will do the same with their regular mobile lineup after Arrow Lake. Why should they do this if they are 18A volume limited. Panther Lake is not a MX chip, it's UPH. There is no On-package memory either based on the Intel slide.

Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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