I think that the topic of the impact of cache and delays on IPC has been developed so much that it is obvious. Let's go ahead and continue the topic of Zen5.
A processor with a 0.2 ms latch can process more instructions per cycle than a processor with a 0.3 ms latch.
Less downtime means the core can accept more instructions (data) and process more of them at the same time.
This is an increase in the number of instructions processed per cycle, or...
Core architecture changes + unified L3 cache as a whole architecture. I don't know how you can still think that L3 was completely irrelevant to IPC.
Not true. If core A 4GHz + VCache compared to core B 4GHz without VCache allows you to get +15% more FPS, this is an increase in the IPC of the...
RaptorLake has no inter-chiplet latency problem and the RAM controller is on the same chip. Thanks to 2MB L2 instead of 1.25MB, RaptorLake gains approximately +4-5% higher IPC.
Zen has a RAM controller on a separate IOD, so it needs larger L3 to compensate, and this is mainly why it benefits...
V Cache is a lot of additional billions of transistors to obtain additional IPC layers from the cores. VCache only allows you to get close to the theoretical peak IPC of a given architecture. To see further gains again, you need a new and more complex core design (to put it very simply).
Everything matters. Games benefit mainly from this.
Just a moment ago you said that you don't see the difference, that each core has direct access to the common L3 of 32MB instead of 16MB and at the same time inter-core communication benefits because it does not have to communicate in the same...
And did I write somewhere that there are no other improvements apart from the cache?
VCache clearly shows that reducing latency in accessing RAM by using it less frequently results in additional IPC gain, which is mainly used by games.
I see this is still a problem.
CCD Zen 2 has 2x CCX(4 cores and 16MB)
(2x 16 MB (total 32 MB)).
The problem is that each Zen2 core only has direct access to 16MB, and another 16MB is connected by a much slower IF.
CCD Zen3 has 1x CCX, i.e. 8 cores and 32MB. This allows each Zen3 core to have...
At what point am I wrong? Enlighten me.
Sorry. My fault. I took this post in the wrong context.
The topic is mainly addressed to the previous speaker who pretends to be an expert and still does not see that the transition from Zen 2 to Zen 3 increases direct access from 16MB to 32MB for each...
You clearly wanted to deny that cache has any effect on IPC, since AMD didn't state that on the slide. While claiming that delays have no impact on IPC.
You were both wrong.
Are you sure it didn't increase L3? Each Zen3 core has direct access to 32 MB instead of just 16 MB like a single Zen2 core. I see the difference, but you don't see it.
Obfuscation? Read previous entries. Previous speakers claim that cache has nothing to do with the increase in IPC. I have provided clear proof that it is quite the opposite and the proof is VCache which can increase a lot of IPC. Not in every application, but the L3 design itself and its...
Why would they add HT to Core 2 when it already provided a large (compared to Core 1) IPC increase, even a gigantic one compared to P4(Netbrust). HT has been added to the expanded and redesigned Nehalem. This was the plan and bargaining chip of the new LGA1366 platform.
C&C:
"VCache provides a notable 33% L3 hitrate increase here. Bringing average hitrate to 78% is more than enough to compensate for the slight L3 latency increase. GHPC enjoys a 9.67% IPC gain from running on the VCache CCD, so the other CCD should fall short even with its higher clock speed."...
It is largely Front-End and Load Store.
I don't know how else to explain it.
If the cache had nothing to do with IPC, the 3DV cache would provide absolutely nothing. And yet he can give a specific boost.
The biggest problem with Zen2 was the division into 2 CCXs, which made communication at...
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