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N
naukkis
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
NPU is exact opposite of FPU. Floating point instructions are varying point so number expression range can be huge, like from 2^-64 to...
Mar 19, 2024
N
naukkis
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
Actually higher leakage in cpu means higher clocking potential. Cpu manufacturers sometimes give golden overclocking samples away that...
Mar 10, 2024
N
naukkis
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
I speculated in risc-v threads that cpu designs should go towards split register file designs. VISC is nothing more than split register...
Mar 9, 2024
N
naukkis
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
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Yeah, Intel should probably just made GoldenCove much bigger and run 40 of them @2Ghz with at least 4-way SMT to be competitive with...
Mar 9, 2024
N
naukkis
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
That's absolutely not core's fault. Intel does pack them that way for being easily add 4-core complexes to existing ring/mesh networks...
Mar 9, 2024
N
naukkis
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
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Intel big cores are just wasted in their server grade cpu's - they are enormous as they are designed to run 6GHz and they are clocked...
Mar 9, 2024
N
naukkis
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
Intel HT is symmetrical threading. Both threads are equal, every other clock cycle instructions are feed from different thread. There...
Mar 8, 2024
N
naukkis
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
.
Those cases where single-thread speed doesn't matter they should drop big cores and use just more e-cores. Actually Intel is doing it...
Mar 8, 2024
N
naukkis
replied to the thread
Discussion
Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads
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Big cores in hybrid designs are there to offer better thread performance. Using HT will nullify that as HT will split core thread...
Mar 8, 2024
N
naukkis
replied to the thread
Question
Greatest x86 innovations?
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Actually 386 protected mode is just same as 286, just expanded to 32bits, with paging unit added. 386 just allows misusing it's...
Mar 2, 2024
N
naukkis
replied to the thread
Discussion
Future ARM Cortex + Neoverse µArchs Discussion
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x86 is hard to translate to any other ISA but Apple and Windows are doing it fine today for aarch64. Arm to risc-V and other way around...
Feb 25, 2024
N
naukkis
replied to the thread
Discussion
Future ARM Cortex + Neoverse µArchs Discussion
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Legacy support ain't so important nowadays - it's pretty much enough that there is emulation layer to support existing software. Google...
Feb 25, 2024
N
naukkis
replied to the thread
Discussion
Future ARM Cortex + Neoverse µArchs Discussion
.
Basic principle should be KISS - keep it simple stupid. At Intel they time after time develop exact opposites of that - IAPX432...
Feb 24, 2024
N
naukkis
replied to the thread
Discussion
Future ARM Cortex + Neoverse µArchs Discussion
.
They made ISA to implement everything compiler could do to made their core forward-proof without recompilation and to make execution...
Feb 24, 2024
N
naukkis
replied to the thread
Discussion
AMD's Future CPU-APU Gone ARM !!!
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Qualcomm proposes basically to make Risc-V AAarch64. That makes sense if they just want to change their ARM64 hardware as easy as...
Feb 24, 2024
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