Afaik Snapdragons enable no SVE, for reasons that are not immediately obvious to me (but variable-length vector machines are a little more of a pain to work with than commonly believed, IME.) I don't think SME even exists in the licensable cores right now.
Lot of extremes in this thread and elsewhere - either M4 is the most amazing thing ever or doomed Apple.
It seems to me like the truth is somewhere in the middle - that the M4 is a decent rev of the M3 architecture with some nice freebies (SME, two additional small cores) and a small clock bump...
Probably a inevitable issue, though - new extensions are added by vendors all the time. I'm not sure what the solution is. SPEC doesn't prohibit submission with whatever ops the user wants, but vendor SPEC submissions are also kinda worthless.
Perhaps, if Geekbench is wedded to the model of...
I put together a quick and dirty clock-normalized comparison spreadsheet between M4 and A17:
I'm using https://browser.geekbench.com/v6/cpu/6010114 for the iPhone data. (Also it only just occurred to me that I could have compared against M3 instead of A17. I am a very stupid lady at times...
I only looked at it briefly, but I think a lot of the gains are SME. The clock-normalized gains for the normal integer-spaghetti subtests against A17 are pretty small, often close to flat.
The benchmark is Affinity Photo's internal bench, which AFAIK is MT.
I'm actually kind of impressed with +50% if it's demonstrated across a reasonably wide set of multithreaded workloads. I don't think that's a bad bump across two gens.
There's also fusion to consider. As you know, "width" is kind of a fuzzy concept, especially with aggressively OoO machines where number of uops executing in a given cycle can greatly exceed the machine's sustained whole-pipe width.
Note that Neoverse V2, which is emphatically an 8-wide core...
Seems like a solid number if it's actually at 2.1GHz, but also like there's a lot of murkiness around it. (Also, isn't it a bit early to be seeing X5 numbers? IIRC final RTL ships only a short while before ARM's annual announcement, no?)
Yeah, Loongarch is the current ISA of Loongson - it looks like a de-legacied MIPS without a lot of the nastiness (delayed braches, hi/lo); from what I've seen it's not a bad ISA design. There are available manuals. The current-gen Loongson, which uses it, is also a very reasonable...
Do you know if there are any docs available? I looked it up and only saw stuff from what seemed like very dubious blogs and "news" sites. One claimed it was a VLIW (and also insisted this was somehow revolutionary.)
Yep. We'll know in weeks.
I don't think we'd be seeing the level of OEM interest that we are if the situation were as bad as some here seem to believe, though. Certainly OEMs were not lining up to ship premium Kaveri or Richland devices. I also freely admit that I have no experience directly...
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