For Matisse that seems to be the case. Either there is a small iGPU on the IO die or there's some other reason why the IO die is the size it is.
Well, it depends on whatever that IO die has a small iGPU or not. AMD wanted to cut some rumors about GPU chiplet for the near future. So Matisse...
I have been very busy lately and it's nice that chiakokhua beat me to it with his illustrations. :) At some point I will also have mine out.
There might still be some server only logic in the Rome IO die that can be removed from the Matisse IO die, but sure, it would still be a very little...
Cache coherency logic is split between different infinity fabric nodes. Here's a pretty good illustration of the Raven Ridge SoC and different Infinity Fabric nodes. There's a cache-coherent master for the CCX and two masters for the GPU. There's also a cache-coherent slave for each memory...
This is still just speculation but if they're using the same organic package (edit: or at least the same basic layout, why would they otherwise put that one chiplet in the corner) for all AM4 SKUs (they could alternatively have different packages for different chiplet configurations) then all...
To be fair, I think it's just a typo and it should have been 32 (or 24) PCI-E lanes.
Personally I have to say that everything makes a lot more sense now than it did when we were talking about half SoC's with DDR4 MCs and IO splitted between dies or many other bifurcated variations. It was still...
He said all a long to take it with a pinch of salt and that it was all rumors, leaks and speculation. He also said in his video that the latest rumors were dropped on him on email and he choose to believe them. His previous speculation about chiplets and IO dies has been very interesting and...
While most of you have already found this, I will post this for those few that haven't spotted this live stream yet:
It should start about in half an hour. Let's hope for some concrete information about 7nm products.
AdoredTV posted a new video on what we should expect from CES 2019:
He still stands by his leak that Ryzen 3000 CPU's (desktop, 7nm, 6-16 cores, AM4) will be announced at CES 2019. The highest end 16 core SKU and all G variants with Navi graphics would be announced later. Previous leaks also...
TSMC 7nm using cobalt for contacts is exactly what raghu78 assumed two weeks ago. So that article is just confirming what Scotten Jones meant by "TSMC 7nm adds cobalt". To say the least, it looks very promising for Zen2 clock speeds.
Since raghu78 should not self-promote his Twitter account, I will do it for him :) (even though I don't have any connections to him or to chiakokhua for that matter):
At this point I was asking if you really thought that the current Rome chiplet (72mm²) has enough room for all the IO required for a full SoC comparable to current Ryzen models.
Then you clarified that you meant that each Rome chiplet might have enough room for half the IO.
I still think...
There's a really interesting interview with David Kanter (from realworldtech.com) on Gamer's Nexus Youtube channel related to this thread:
I'm adding it here since someone in here might not have yet seen it. I'm currently watching it myself.
Addition: David Kanter talks in the interview...
Ok, here's an illustration of the speculative 1xDDR4 and half the IO per die design (based on what moinmoin and dnavas suggested):
As you can see there would likely be the following core configurations:
Ryzen 3 (6C): (3 + 3) + (0 + 0), 1Ch DDR4
Ryzen 5 (8C): (2 + 2) + (2 + 2), 2Ch DDR4
Ryzen...
As I undestood it, there is no IO die, just two equal sized CPU dies containing half of the IO both. There's only one IF-link between them so that's one IF hop. And that's basically all it is. 6C model would only have one (single channel) DDR4 controller while other models would have two. I'm...
That's exactly right. It would cost much less for them to differentiate their products using different 14nm IO dies (i.e. main dies) than having many different 7nm designs. Also 7nm would be best utilized having large caches and tightly packed cores (execution units) rather than more IO that...
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