Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

uzzi38 · May 1, 2024

Yeah recently another private tech Twitter account did a big purge of many of their followers because of people sharing screenshots of what they posted. Given we know the rumour outlets do scan over these forums, it would be wise not to give them a chance to screw over someone else.

Joe NYC · May 1, 2024

Ghostsonplanets said:
When comparing to TGL that shipped >100M in a bit more than a year and Alder Lake which shipped >50M, MTL numbers indeed are on the very low side.

Still, 40M should be nothing to snub at. Specially in a recovering market and given LNL and ARL should be a small part of it for this year. Intel will need to increase packaging capabilities soon due to the ramp-up of more tiled designs.

Another number Intel floated is 100m AI PCs in 2 years, which means 60m for 2025.

2025 would be MTL + ARL + LNL + Panther Lake (or whatever the code name is?). That just does not sound right to me...

Philste · May 1, 2024

uzzi38 said:
Yeah recently another private tech Twitter account did a big purge of many of their followers because of people sharing screenshots of what they posted. Given we know the rumour outlets do scan over these forums, it would be wise not to give them a chance to screw over someone else.

Got it. Although I feel that someone of WccfTech has direct access to his Tweets, they put out the news nearly directly after he tweeted it and sometimes before it arrived here. But it's definitely like you said with some other Twitter Persons.

DrMrLordX · May 1, 2024

Joe NYC said:
But it is also worth speculating how much higher the capacity is to fabricate the silicon dies above this limit. Internally and how much of additional silicon Intel ordered from TSMC for other tiles.

Until Intel switches to High NA nodes, their wafer volume is gonna be pretty low. At this point I'd like to point back to the old Mizuho report that predicted this very problem and say "they told us so".

SpudLobby · May 1, 2024

DrMrLordX said:
Until Intel switches to High NA nodes, their wafer volume is gonna be pretty low. At this point I'd like to point back to the old Mizuho report that predicted this very problem and say "they told us so".

Do we know High NA will really improve their wafer volume capacity?

I think it was speculated to be true based on the directed assembly tech right?

Tbh they might also improve wafer volumes as an effect of time once they get to High NA: just because they’ll be getting better with EUV broadly and process nodes (they’ll have to, to court customers).

SpudLobby · May 1, 2024

Markfw said:
None of the above.... IMO, they both had places where they won, but overall it really was pretty even. Thats the part I disagree with the reviewer on. But I will agree that its a stopgap by both for next years Zen 5 vs Lunar lake that we should wait for.

Yeah I basically think it’s pretty similar right now or at least the smallest gap in a good while on mobile chips from these two.

AMDK11 · May 1, 2024

In the LionCove diagram, there are 24 positions in the decoder and uop cache fields.

As I mentioned earlier, GoldenCove has 14 items, 6 of which are from the decoder and 8 from the UOP cache.

My theory is that either Intel will surprise and LionCove has a 66% wider decoder, i.e. 10-way + 14 is shipped from UOP. Otherwise it is 8 from the decoder and 16 from the uop.

Earlier rumors were more related to 8-Way Dispatch/Rename, which does not rule out a 10-way decoder.

One more thought about LionCove. Dedicated 4 ports for the FPU part, couldn't they be FP-ALU? In total, this would give 10 ALUs for e.g. SMT4 (there were rumors that it was disabled and is physically in the core).

Just a loose thought, nothing more. If this happened, LionCove would provide a fairly safe advantage for Intel in terms of the microarchitecture of P cores, or IPC.

This is as part of continuing the discussion on such an important topic as LionCove.
I see no one has touched on the LionCove diagram, which reveals some microarchitectural details or confirms or denies some rumors. This data raises further questions. And this is highly sought-after data.

I wonder if anyone has already taken the LionCove diagram to analyze the new core and what consequences it may have for Intel's new approach to P cores.

Edit:
Does a 10-way decoder for LionCove sound so abstract considering the 9-way (3x 3-Way) for Skymont?

This is purely hypothetical:
GoldenCove decoder 6-Way vs LionCove decoder 10-Way (+66%)
GoldenCove shipping from UOP cache 8 vs LionCove shipping from UOP cache 14 (+75%)
GoldenCove 12 execution ports vs LionCove 18 execution ports (+50%)

Joe NYC · May 1, 2024

DrMrLordX said:
Until Intel switches to High NA nodes, their wafer volume is gonna be pretty low. At this point I'd like to point back to the old Mizuho report that predicted this very problem and say "they told us so".

Intel needs EUV of any kind. Perhaps Intel will use the High NA on their current nodes too. Maybe Intel logic is that if High NA is going to be used for everything in the future, then why not buy the bullet and not order high priced Hith NA machines instead of regular EUV.

So, intel is still stuck in the same mode for their "foundry", that it is not really a foundry. When TSMC builds a fab on say for 7nm, it typically stays on 7nm forever, and TSMC can maximize usage of the tools, for highest return on capital invested.

Intel, in the past, kept transitioning to newer and newer nodes, to have maximum amount of capacity on (what was then) a leading node. The whole scheme was paid for by monopoly profits.

If Intel does not foresee much foundry business for Intel 4 through 18A, then it may make sense for Intel to only buy High NA from now on. The problem is that the monopoly profits to pay for all of this are not there any more...

Henry swagger · May 1, 2024

AMDK11 said:
In the LionCove diagram, there are 24 positions in the decoder and uop cache fields.

As I mentioned earlier, GoldenCove has 14 items, 6 of which are from the decoder and 8 from the UOP cache.

My theory is that either Intel will surprise and LionCove has a 66% wider decoder, i.e. 10-way + 14 is shipped from UOP. Otherwise it is 8 from the decoder and 16 from the uop.

Earlier rumors were more related to 8-Way Dispatch/Rename, which does not rule out a 10-way decoder.

One more thought about LionCove. Dedicated 4 ports for the FPU part, couldn't they be FP-ALU? In total, this would give 10 ALUs for e.g. SMT4 (there were rumors that it was disabled and is physically in the core).

Just a loose thought, nothing more. If this happened, LionCove would provide a fairly safe advantage for Intel in terms of the microarchitecture of P cores, or IPC.

This is as part of continuing the discussion on such an important topic as LionCove.
I see no one has touched on the LionCove diagram, which reveals some microarchitectural details or confirms or denies some rumors. This data raises further questions. And this is highly sought-after data.

I wonder if anyone has already taken the LionCove diagram to analyze the new core and what consequences it may have for Intel's new approach to P cores.

Edit:
Does a 10-way decoder for LionCove sound so abstract considering the 9-way (3x 3-Way) for Skymont?

This is purely hypothetical:
GoldenCove decoder 6-Way vs LionCove decoder 10-Way (+66%)
GoldenCove shipping from UOP cache 8 vs LionCove shipping from UOP cache 14 (+75%)
GoldenCove 12 execution ports vs LionCove 18 execution ports (+50%)

How much ipc does this bring at iso speed vs golden cove ?

Saylick · May 1, 2024

AMDK11 said:
I wonder if anyone has already taken the LionCove diagram to analyze the new core and what consequences it may have for Intel's new approach to P cores.

Edit:
Does a 10-way decoder for LionCove sound so abstract considering the 9-way (3x 3-Way) for Skymont?

This is purely hypothetical:
GoldenCove decoder 6-Way vs LionCove decoder 10-Way (+66%)
GoldenCove shipping from UOP cache 8 vs LionCove shipping from UOP cache 14 (+75%)
GoldenCove 12 execution ports vs LionCove 18 execution ports (+50%)

I certainly don't have the background to tell you what consequences the increases will produce, but I do know that just widening the core in every dimension doesn't automatically translate to a proportional or even square root increase in performance. In the end, I do think you're onto something here because I have yet to see someone sleuth into analyzing the rendering as much as you have.

uzzi38 said:
Yeah recently another private tech Twitter account did a big purge of many of their followers because of people sharing screenshots of what they posted. Given we know the rumour outlets do scan over these forums, it would be wise not to give them a chance to screw over someone else.

My cynicism is also giving me the gut feeling that WTFTech is probably keeping tabs on this thread and will make an article the moment someone here decides to condense those Lion Cove findings into a nice architectural diagram. I doubt they'd spend the effort piecing a story together from scattered musings, but if you give them a succinct summary even if it's all speculation/conjecture? Ohh boy, off to the printers they'll go.

controlflow · May 1, 2024

Joe NYC said:
Intel needs EUV of any kind. Perhaps Intel will use the High NA on their current nodes too. Maybe Intel logic is that if High NA is going to be used for everything in the future, then why not buy the bullet and not order high priced Hith NA machines instead of regular EUV.

So, intel is still stuck in the same mode for their "foundry", that it is not really a foundry. When TSMC builds a fab on say for 7nm, it typically stays on 7nm forever, and TSMC can maximize usage of the tools, for highest return on capital invested.

Intel, in the past, kept transitioning to newer and newer nodes, to have maximum amount of capacity on (what was then) a leading node. The whole scheme was paid for by monopoly profits.

If Intel does not foresee much foundry business for Intel 4 through 18A, then it may make sense for Intel to only buy High NA from now on. The problem is that the monopoly profits to pay for all of this are not there any more...

Only Intel 3 and 18A are foundry nodes. As you know Intel 4 and 20A don't even feature full libraries, they are more like stepping stones and development nodes that will be relatively short lived. The actual foundry nodes 18A and 3 are supposed to be long lasting and get updates beyond what is initially available. Additionally, they will also keep Intel 7 and 16 around as foundry nodes and they are developing a "12nm" node with UMC.

It is very cost inefficient to develop nodes like 4 and 20A and move on fairly quickly from them but this is the price that Intel must pay to catch up. There is really no way around that and one look at Intel's balance sheet and most recent CapEx and cashflow shows the brutal price they are paying.

maddie · May 1, 2024

Joe NYC said:
Intel needs EUV of any kind. Perhaps Intel will use the High NA on their current nodes too. Maybe Intel logic is that if High NA is going to be used for everything in the future, then why not buy the bullet and not order high priced Hith NA machines instead of regular EUV.

So, intel is still stuck in the same mode for their "foundry", that it is not really a foundry. When TSMC builds a fab on say for 7nm, it typically stays on 7nm forever, and TSMC can maximize usage of the tools, for highest return on capital invested.

Intel, in the past, kept transitioning to newer and newer nodes, to have maximum amount of capacity on (what was then) a leading node. The whole scheme was paid for by monopoly profits.

If Intel does not foresee much foundry business for Intel 4 through 18A, then it may make sense for Intel to only buy High NA from now on. The problem is that the monopoly profits to pay for all of this are not there any more...

High NA should only be used for the first steps in the fabrication process. As you progress up the die layers, you can use previous cutting edge machines that will be cheaper to operate.

Rinse & repeat for the successor to high NA, displacing everything another step.

In other words, using High NA for all is too costly in a free market situation.

repoman27 · May 2, 2024

DrMrLordX said:
Until Intel switches to High NA nodes, their wafer volume is gonna be pretty low. At this point I'd like to point back to the old Mizuho report that predicted this very problem and say "they told us so".

Intel D1X Mod3 in Oregon and Fab 34 in Leixlip, Ireland are both fully tooled up with EUV equipment and supposedly in high-volume production using the Intel 4 process. At an estimated capacity of 12 kwpm for D1X and 22 kwpm for Fab 34, that's a combined 34 kwpm of Intel 4 capacity. Per Mizuho's estimates, Intel should have had a capacity of 20 kwpm by 2023 and have taken delivery of 20 EUV litho machines, which would be enough to accommodate up to 45 kwpm of Intel 4 going forward. Those were completely reasonable projections.

Now I ask you, "What is Intel doing with all those wafer starts?" As far as I can tell, two of Intel's largest and most expensive fabs to date are sitting mostly idle because Intel 4 doesn't have enough tape outs. Can someone please point me to an earnings call where Intel has said that they are capacity constrained on Intel 4 or EUV in general? If so why? They still aren't making anything in volume that even requires EUV!

Intel has serious issues with manufacturing at the moment, but lack of EUV litho tools is not one of them.

Doug S · May 2, 2024

Joe NYC said:
Intel needs EUV of any kind. Perhaps Intel will use the High NA on their current nodes too. Maybe Intel logic is that if High NA is going to be used for everything in the future, then why not buy the bullet and not order high priced Hith NA machines instead of regular EUV.

High NA scanners cost more than twice as much (and are much larger and use more power and are in very short supply and are brand new and more likely to have teething issues) so using them for process steps where they provide no benefit over regular EUV scanners makes no sense. I mean, you could make the same argument about buying only EUV and no longer buying DUV, since you can use EUV for anything DUV can do. I think you can see why that would be a bad idea.

igor_kavinski · May 2, 2024

Doug S said:
High NA scanners cost more than twice as much (and are much larger and use more power and are in very short supply and are brand new and more likely to have teething issues)

I read somewhere (maybe AT front page?) that these newfangled scanners get out of sync or the mirror gets degraded pretty quickly so they demand frequent maintenance and hence incur more downtime. Depending solely on these scanners, you would need a fair bit of redundancy and hence even more upfront cost to ensure that production doesn't get halted due to scanner downtime.

SpudLobby · May 2, 2024

RE: High NA:

The reason Intel is going all-in on High NA scanners despite the fact that it really doesn’t make much sense in the near term due to the cost is their directed self-assembly tech is ahead of the game and can dramatically reduce the exposures needed from EUV if it pans out. It’s the key to 14A and it’s use of high NA it seems.

Would be a tremendous advantage (and DSA works for regular EUV exposures, too) if it pans out.

Intel’s 14A Magic Bullet: Directed Self-Assembly (DSA)

How High-NA EUV can be economically viable at the 1.4nm process node

www.semianalysis.com

Gideon · May 2, 2024

A side-slide to Machine Learning again. It looks that newer models are more-and-more "gamed" to fit the benchmarks (That will inevitably end in the training data, as it more-or-less uses the entire internet):

https://twitter.com/x/status/1785877026794356858

Phi3 and Mistral were the biggest culprits (losers) when run on a similar (but private) benchmark.

Oh and btw, a radically different paper on how to do Machine Learning (among other things9 just dropped and took the field by a storm. One that is much more reasonable for a human (and it's easier to inject domain-knowledge):

Thread by @ZimingLiu11 on Thread Reader App

@ZimingLiu11: MLPs are so foundational, but are there alternatives? MLPs place activation functions on neurons, but can we instead place (learnable) activation functions on weights? Yes, we KAN! We propose Kolmogoro...…

threadreaderapp.com

The abstract:

Inspired by the Kolmogorov-Arnold representation theorem, we propose Kolmogorov-Arnold Networks (KANs) as promising alternatives to Multi-Layer Perceptrons (MLPs). While MLPs have fixed activation functions on nodes ("neurons"), KANs have learnable activation functions on edges ("weights"). KANs have no linear weights at all -- every weight parameter is replaced by a univariate function parametrized as a spline. We show that this seemingly simple change makes KANs outperform MLPs in terms of accuracy and interpretability. For accuracy, much smaller KANs can achieve comparable or better accuracy than much larger MLPs in data fitting and PDE solving. Theoretically and empirically, KANs possess faster neural scaling laws than MLPs. For interpretability, KANs can be intuitively visualized and can easily interact with human users. Through two examples in mathematics and physics, KANs are shown to be useful collaborators helping scientists (re)discover mathematical and physical laws. In summary, KANs are promising alternatives for MLPs, opening opportunities for further improving today's deep learning models which rely heavily on MLPs.

This might change the market substantially in the coming years.

DrMrLordX · May 2, 2024

Joe NYC said:
Intel needs EUV of any kind. Perhaps Intel will use the High NA on their current nodes too.

20a and 18a were supposed to be High NA nodes when they were announced. Intel has since backtracked. There are good reasons not to use High NA such as reticle size limits.

repoman27 said:
Intel D1X Mod3 in Oregon and Fab 34 in Leixlip, Ireland are both fully tooled up with EUV equipment and supposedly in high-volume production using the Intel 4 process. At an estimated capacity of 12 kwpm for D1X and 22 kwpm for Fab 34, that's a combined 34 kwpm of Intel 4 capacity. Per Mizuho's estimates, Intel should have had a capacity of 20 kwpm by 2023 and have taken delivery of 20 EUV litho machines, which would be enough to accommodate up to 45 kwpm of Intel 4 going forward. Those were completely reasonable projections.

Now I ask you, "What is Intel doing with all those wafer starts?" As far as I can tell, two of Intel's largest and most expensive fabs to date are sitting mostly idle because Intel 4 doesn't have enough tape outs. Can someone please point me to an earnings call where Intel has said that they are capacity constrained on Intel 4 or EUV in general? If so why? They still aren't making anything in volume that even requires EUV!

Intel has serious issues with manufacturing at the moment, but lack of EUV litho tools is not one of them.

I'm glad you brought up those numbers and aligned them thusly to make a good point. Even the Mizuho report's figures didn't prepare us for a future where a delayed Meteor Lake would consume maybe 20k wafers of Intel 4 through March 2024. Too many projects got moved off Intel 4. Maybe Intel 3 will turn things around, especially since it's supposed to be an actual foundry node (unlike Intel 4 which has the Ericsson RAN processor and . . . not much else).

maddie · May 2, 2024

SpudLobby said:
RE: High NA:

The reason Intel is going all-in on High NA scanners despite the fact that it really doesn’t make much sense in the near term due to the cost is their directed self-assembly tech is ahead of the game and can dramatically reduce the exposures needed from EUV if it pans out. It’s the key to 14A and it’s use of high NA it seems.

Would be a tremendous advantage (and DSA works for regular EUV exposures, too) if it pans out.

Intel’s 14A Magic Bullet: Directed Self-Assembly (DSA)

How High-NA EUV can be economically viable at the 1.4nm process node

www.semianalysis.com

Bolded, do have some firm info on this?

According to the SA article, this tech is being researched for quite a long time and not an Intel exclusive, though they might have a unique breakthrough.

Can we be certain that Intel is not doing the whole 10nm, overreaching, have to return to leadership position strategy, that backfired so badly for them?

SpudLobby · May 2, 2024

maddie said:
Bolded, do have some firm info on this?

According to the SA article, this tech is being researched for quite a long time and not an Intel exclusive, though they might have a unique breakthrough.

Can we be certain that Intel is not doing the whole 10nm, overreaching, have to return to leadership position strategy, that backfired so badly for them?

It does claim they’re ahead on this pretty directly by way of the breakthrough and their High NA use being non-R&D exclusive but yeah shouldn’t have bolder.

repoman27 · May 2, 2024

DrMrLordX said:
20a and 18a were supposed to be High NA nodes when they were announced. Intel has since backtracked. There are good reasons not to use High NA such as reticle size limits.

I'm glad you brought up those numbers and aligned them thusly to make a good point. Even the Mizuho report's figures didn't prepare us for a future where a delayed Meteor Lake would consume maybe 20k wafers of Intel 4 through March 2024. Too many projects got moved off Intel 4. Maybe Intel 3 will turn things around, especially since it's supposed to be an actual foundry node (unlike Intel 4 which has the Ericsson RAN processor and . . . not much else).

Just to put it in perspective, Intel currently has enough fab capacity to crank out 180 million MTL 6+8 CPU tiles in the next 12 months, enough to put one in every low-power x86 device sold in a typical year, while operating their fabs at 60% capacity and with defect densities of 0.25 / cm².

That's clearly not happening though. I've been out of the loop for a while... what designs does Intel even have planned for Intel 4/3 at this point?

dullard · May 2, 2024

repoman27 said:
That's clearly not happening though. I've been out of the loop for a while... what designs does Intel even have planned for Intel 4/3 at this point?

That isn't happening since Intel is more packaging constrained for Meteor Lake at this point.

This image is getting a little old (Aug 2023), but it shows Intel's plans. Now there are a lot more announced products on 18A than when Intel generated this image.

That said, there isn't just one Intel 3. They have announced Intel 3, 3-T (3D stacking), 3-E (extended features), and 3-PT (performance improvement + 3D stacking).

repoman27 · May 2, 2024

dullard said:
That isn't happening since Intel is more packaging constrained for Meteor Lake at this point.

This image is getting a little old (Aug 2023), but it shows Intel's plans. Now there are a lot more announced products on 18A than when Intel generated this image.

That said, there isn't just one Intel 3. They have announced Intel 3, 3-T (3D stacking), 3-E (extended features), and 3-PT (performance improvement + 3D stacking).

Is Intel actually packaging constrained, or just demand constrained for MTL? Fab 42 in Arizona is where they were doing the MTL packaging, and it's huge. Even complex packaging like MTL should take way less time and space than processing wafers. The only thing I can imagine being a constraint is fabbing all of the passive interposers, which they insist on referring to as "Foveros" despite lacking any active circuitry.

It looks like Sierra Forest and Granite Rapids should keep D1X Mod3 and Fab 34 busy though, and those CPU tiles are decently sized, so the process probably is working OK, or they wouldn't have gone that big. And they're using EMIB for the package so probably fewer constraints there. Anyone know if the HSIO tiles are also Intel 3 or something else?

SiliconFly · May 2, 2024

dullard said:
That isn't happening since Intel is more packaging constrained for Meteor Lake at this point.

This image is getting a little old (Aug 2023), but it shows Intel's plans. Now there are a lot more announced products on 18A than when Intel generated this image.
<image>

That said, there isn't just one Intel 3. They have announced Intel 3, 3-T (3D stacking), 3-E (extended features), and 3-PT (performance improvement + 3D stacking).
<image>

It appears they're going to use Intel 3 mainly for SRF, GNR & Foveros base tiles.

dullard · May 2, 2024

repoman27 said:
Is Intel actually packaging constrained, or just demand constrained for MTL? Fab 42 in Arizona is where they were doing the MTL packaging, and it's huge. Even complex packaging like MTL should take way less time and space than processing wafers. The only thing I can imagine being a constraint is fabbing all of the passive interposers, which they insist on referring to as "Foveros" despite lacking any active circuitry.

I thought that their high volume Foveros packaging is in fab 9 that just opened. I haven't seen if it is all up and running or just partway there. Do you have information on Fab 42 doing Foveros? https://www.intel.com/content/www/us/en/newsroom/news/intel-opens-fab-9-new-mexico.html#gs.8siodd

Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Senior member

Attachments

Platinum Member

Platinum Member

Member

Lifer

Senior member

Senior member

Senior member

Platinum Member

Senior member

Diamond Member

Member

Diamond Member

Senior member

Platinum Member

Lifer

Senior member

Golden Member

Lifer

Diamond Member

Senior member

Senior member

Elite Member

Senior member

Golden Member

Elite Member