Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[SiliconFly]

Is Intel actually packaging constrained, or just demand constrained for MTL? Fab 42 in Arizona is where they were doing the MTL packaging, and it's huge.

Pat mentioned that "they're constrained by wafer level assembly supply, which is impacting their ability to meet demand for Meteor Lake". Not sure whether it's is a Fab 42 issue... but I was under the impression that its more of a New Mexico Fab 9 issue as it's just ramping up.

 

[SiliconFly]

I thought that their high volume Foveros packaging is in fab 9 that just opened. I haven't seen if it is all up and running or just partway there. Do you have information on Fab 42 doing Foveros? https://www.intel.com/content/www/us/en/newsroom/news/intel-opens-fab-9-new-mexico.html#gs.8siodd

Agree. Even I think it's a Fab 9 issue. Think we can expect good volume in Q3/Q4.

Funny how things work with Intel. They're gonna flood all store shelves with MTL this year end when it's already outdated!

 

[Doug S]

It does claim they’re ahead on this pretty directly by way of the breakthrough and their High NA use being non-R&D exclusive but yeah shouldn’t have bolder.

Yeah I read that story shortly after it came out, but it is rather worrying that Intel seems to be betting the company on being able to take DSA to mass production. I sure hope they have a backup plan if it ends up having too high a defect rate or whatever when they go from running a few wafers on a small development line to trying to mass produce 14A wafers.

 

[SpudLobby]

Yeah I read that story shortly after it came out, but it is rather worrying that Intel seems to be betting the company on being able to take DSA to mass production. I sure hope they have a backup plan if it ends up having too high a defect rate or whatever when they go from running a few wafers on a small development line to trying to mass produce 14A wafers.

Yeah I agree. I mean do they have non-high NA scanners though?

My biggesst hope for Intel is getting denser cells somewhat competitive for low power (Read: still some “HPC” stuff but not so leaky and area-heavy) with 18A derivatives, and ideally then some more meaningful parity with 14A, while having had a head start on backside power delivery over TSMC and Sammy which can’t hurt if they play their cards right.

But if they primarily have high NA at this point or far too many as a % of scanners and they’re betting on DSA, they’d better hope it works out.

 

[Hulk]

Now that Intel's feature size is basically meaningless it seems as though Intel 7nm is actually going to be 4 steppings to be known as Intel 4, Intel 3, 20A, and 18A. Back in the 10nm days these would simply have been called 7, 7+, 7++, 7+++. This is good marketing as Intel gets to look like they are cranking out smaller and smaller nodes at an amazing rate.

Testing will show us if these nodes are actually new and not just refinements/steppings. So far Intel 4 in MTL seems to be very comparable to the last Intel 10+++++++++++++++++.

Fool me once Intel... you know the rest.

 

[Ghostsonplanets]

Intel 7, Intel4/3 and Intel 20A/18A are wholly separated nodes. They're unrelated to Intel 7 and aren't what we used to call + (Pluses) in the past.

Intel 7 by itself is already 10nm++++
Intel 10nm - Cannon Lake
Intel 10nm + (renamed to 10nm) - Ice Lake/SP
Intel 10nm ++ (renamed to 10nm SuperFin) - Tiger Lake, Intel DG1
Intel 10nm +++ (renamed to Intel 7/Previously also 10nm Enhanced SuperFin|ESF) - Alder Lake, Sapphire Rapids
Intel 10nm ++++ (renamed to Intel 7 Ultra) - Raptor Lake, Emerald Rapids.

Edit: Just read it again an saw that you were talking about Intel 7nm, what is currently known as Intel 4/3. Point still stands though. The closest you can call a + is Intel 3. I20A and I18A are wholly different from I4/I3, even if they might retain some characteristics.

 

[Henry swagger]

https://twitter.com/x/status/1786078746023452915

Intel already had the best memory controller. Arrow will have a updated controller 10k oc is possible they wont need cache spamming to keep the gaming ctown 😁👍

 

[Hulk]

Intel 7, Intel4/3 and Intel 20A/18A are wholly separated nodes. They're unrelated to Intel 7 and aren't what we used to call + (Pluses) in the past.

Intel 7 by itself is already 10nm++++
Intel 10nm - Cannon Lake
Intel 10nm + (renamed to 10nm) - Ice Lake/SP
Intel 10nm ++ (renamed to 10nm SuperFin) - Tiger Lake, Intel DG1
Intel 10nm +++ (renamed to Intel 7/Previously also 10nm Enhanced SuperFin|ESF) - Alder Lake, Sapphire Rapids
Intel 10nm ++++ (renamed to Intel 7 Ultra) - Raptor Lake, Emerald Rapids.

Edit: Just read it again an saw that you were talking about Intel 7nm, what is currently known as Intel 4/3. Point still stands though. The closest you can call a + is Intel 3. I20A and I18A are wholly different from I4/I3, even if they might retain some characteristics.

I meant to write Intel 4 where I wrote Intel 7. I fixed that.

I believe you of course but unless I see actual improvements in the nodes when it comes to efficiency then who cares what they call them?

I don't see much difference between Intel 4 (7nm) and Intel 7 (10+++++++++++++++++). MTL really only shows efficiency gains when only the SoC is powered up and that seems to be more of an architectural improvement.

We shall see how great these new Intel nodes are. So far Intel 4 hasn't impressed me. Am I missing some metrics that show it to be much improved over Intel 7? I am open to changing my opinion. I think MTL is a definite improvement over RPL for mobile, but as I wrote above it seems to be more due to being able to shut down tiles rather than process improvement.

 

[repoman27]

I thought that their high volume Foveros packaging is in fab 9 that just opened. I haven't seen if it is all up and running or just partway there. Do you have information on Fab 42 doing Foveros? https://www.intel.com/content/www/us/en/newsroom/news/intel-opens-fab-9-new-mexico.html#gs.8siodd

Well, clearly Intel wasn't planning on packaging Meteor Lake in a facility that wasn't even going to be finished until a year after the intended launch date.

But also, my bad regarding Fab 42. MTL was actually being assembled at CH4 in Arizona, which is a much smaller facility. They showed this publicly when CNET took a tour of Fab 42 back in Nov 2021: https://www.cnet.com/pictures/a-look-inside-intels-mammoth-arizona-chipmaking-fab/

CH4 was also where Ponte Vecchio was assembled. But the wafers for the base tiles were being made in New Mexico at Fab 11X, so they converted the old Fab 9 next to it into a new advanced packaging and assembly facility. If you watch the b-roll from the bottom of that Intel newsroom post you linked to about the Fab 9 opening, you can get a little bit of a feel for where they were at back in January.

edit: Intel also does Foveros in the 400,000 sq.ft. manufacturing support building (MSB) next to D1X in Oregon. Some footage here (curious what product that is that they show towards the end of the video—ARL?):

And apparently Fab 9 and Fab 11X are still being tooled up, per an April 15, 2024 update here: https://www.intel.com/content/www/u...s-intel-10-largest-construction-projects.html

 

[igor_kavinski]

10k oc is possible they wont need cache spamming to keep the gaming ctown 😁👍

Yes, they currently own the crown in crashing games.

 

[Doug S]

Yeah I agree. I mean do they have non-high NA scanners though?

Of course they do. They are using "regular NA" EUV for Intel 4, 3, 20A and 18A.

At some point ASML will be able to meet demand for EUV and the order backlog will begin to shrink. Not sure if they have reached that already, but I did read recently that ASML's overall order backlog is half what it was last year - though obviously the big reason there is China trying to order as many DUV machines as they can before they're cut off.

But assuming ASML has or soon will begin reducing the EUV backlog Intel would be able to throw in some extra orders if they reached a point where they had to flip the "oops DSA isn't the panacea we hoped it was, time for plan B" switch.

 

[DrMrLordX]

Now that Intel's feature size is basically meaningless it seems as though Intel 7nm is actually going to be 4 steppings to be known as Intel 4, Intel 3, 20A, and 18A. Back in the 10nm days these would simply have been called 7, 7+, 7++, 7+++. This is good marketing as Intel gets to look like they are cranking out smaller and smaller nodes at an amazing rate.

Testing will show us if these nodes are actually new and not just refinements/steppings. So far Intel 4 in MTL seems to be very comparable to the last Intel 10+++++++++++++++++.

Fool me once Intel... you know the rest.

It does seem possible that 20a may not be that radically different/better than Intel 3, though many bristle at the notion that 20a and 18a won't be distinct nodes (rather than a + node). It does seem like Gelsinger is slinging more than a little bs.

 

[Tigerick]

https://twitter.com/x/status/1786078746023452915

Intel already had the best memory controller. Arrow will have a updated controller 10k oc is possible they wont need cache spamming to keep the gaming ctown 😁👍

You should use the term used to cause due to 4-tile design, Meteor Lake is having worst memory latency as tested here. I don't think ARL will change that, maybe PTL with integrated MC will let Intel regain the leadership.

 

[Tigerick]

Just to put it in perspective, Intel currently has enough fab capacity to crank out 180 million MTL 6+8 CPU tiles in the next 12 months, enough to put one in every low-power x86 device sold in a typical year, while operating their fabs at 60% capacity and with defect densities of 0.25 / cm².

That's clearly not happening though. I've been out of the loop for a while... what designs does Intel even have planned for Intel 4/3 at this point?

Let's see:

1. ARL-U's tCPU
2. Sierra Forest
3. Granite Rapids
4. PTL's 4Xe tGPU
5. Upcoming NV ARM SoC

Yep, IF will keep expanding IP of Intel 3 process. It's going to be long term process for IF.

 

[igor_kavinski]

Yep, IF will keep expanding IP of Intel 3 process. It's going to be long term process for IF.

IFS is better when referring to Intel Foundry.

 

[Tigerick]

IFS is better when referring to Intel Foundry.

I know it sounds better, but Intel has changed the name, so what should we refer IF or IFS?

 

[Ghostsonplanets]

@Tigerick do you have any info about PTL-U core configuration? Since ADL, the U series has adopted a 2+8 configuration while P/H was 6+8. Now that PTL-H adopts a 4+8+4 configuration, it makes me wonder how Intel will shape the U series. Maybe 2P+ 4E + 4LPE?

 

[igor_kavinski]

I know it sounds better, but Intel has changed the name, so what should we refer IF or IFS?

IFS would be less ambiguous coz IF is often used for Infinity Fabric around here.

 

[igor_kavinski]

Now that PTL-H adopts a 4+8+4 configuration

What's going on with them? First they have 4P+4 LPE in LNL and then they decide to add E-cores to the mix again? MTL wasn't lesson enough for them?

 

[Tigerick]

@Tigerick do you have any info about PTL-U core configuration? Since ADL, the U series has adopted a 2+8 configuration while P/H was 6+8. Now that PTL-H adopts a 4+8+4 configuration, it makes me wonder how Intel will shape the U series. Maybe 2P+ 4E + 4LPE?

Good question, I just got reply from my source. You are not going to believe it. PTL-U going to use 4+0+4 configuration. Maybe Intel wants to treat PTL-U as Lunar Laker successor...

 

[Tigerick]

What's going on with them? First they have 4P+4 LPE in LNL and then they decide to add E-cores to the mix again? MTL wasn't lesson enough for them?

And remove e cores again to get 4+4 configuration back in PTL-U..

 

[Tigerick]

Good question, I just got reply from my source. You are not going to believe it. PTL-U going to use 4+0+4 configuration. Maybe Intel wants to treat PTL-U as Lunar Laker successor...

Due to PTL-U GPU is using 4 XE cores made by Intel 3, the graphics performance would be slower than LNL. That's mean PTL-U is positioned slightly below LNL

 

[Ghostsonplanets]

What's going on with them? First they have 4P+4 LPE in LNL and then they decide to add E-cores to the mix again? MTL wasn't lesson enough for them?

Efficiency. For power limited designs, the less cores dividing the power budget, the better. Specially for Intel which has pretty hungry P cores.

Good question, I just got reply from my source. You are not going to believe it. PTL-U going to use 4+0+4 configuration. Maybe Intel wants to treat PTL-U as Lunar Laker successor...

Now that puts a big smile in my face😁. So basically PTL-U is a LNL with smaller but higher clocked iGPU (Newer uArch), bigger NPU and without the MoP cost adder. And also being mainly fabbed on Intel Foundry (Only the PCD tile being external).

If so, this is Intel best move in ages. Basically making LNL power enhancements available to mainstream consumers while having a much cleaner tile design and greatly reducing external foundry. If I am Gelsinger, I would be fast-tracking PTL (Even if only the U SKU) as fast as possible for a Q3 25 release.

 

[igor_kavinski]

If so, this is Intel best move in ages. Basically making LNL power enhancements available to mainstream consumers while having a much cleaner tile design and greatly reducing external foundry. If I am Gelsinger, I would be fast-tracking PTL (Even if only the U SKU) as fast as possible for a Q3 25 release.

Without MoP, is Intel gonna be able to tame the RAM latency for PTL-U? That's how they ruined MTL-U and MTL-H.

 

[Ghostsonplanets]

Due to PTL-U GPU is using 4 XE cores made by Intel 3, the graphics performance would be slower than LNL. That's mean PTL-U is positioned slightly below LNL

Make sense. It's 32 EU X 64 EU. Should be higher clocked and it's based on Celestial, so some uArch enhancements over LNL BMG.

Seems like Intel play with U series GPU tile is to make the smallest tile possible while extracting as much performance. It's an economical play that is a right decision to be made.

MTL-U 4 Xe Core already matched or beat Iris Xe 8 Xe while reducing area. So PTL-U 4 Xe³ core should outperform MTL-U while also reducing area.