Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Page 306 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.
Toggle sidebar Toggle sidebar
T

Tigerick

Senior member
Apr 1, 2022
679
559
106






As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Arrow Lake Refresh (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXDesktop OnlyMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025		Q4 2025 ?Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E8P + 32E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ??8 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15



Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

Attachments

  • PantherLake.png
    283.5 KB · Views: 23,969
  • LNL.png
    881.8 KB · Views: 25,441
Last edited:
Reactions: Hans Gruber, SiliconFly, igor_kavinski and 9 others
Sort by date Sort by votes
N

naukkis

Senior member
Jun 5, 2002
722
610
136
DavidC1 said:
No. If anything uop caches will be sharing the fate of Hyperthreading and be axed in the future.

Uop caches are a remnant of the extreme clock focus of Netburst. Rather than thinking it brings more performance, you should think of it as maintaining performance while allowing it to raise clocks.
Click to expand...

Uop cache is about that energy efficiency difference between decoding instruction and fetching it from mop cache. MOP cache will take silicon space so for area efficiency it's better without but for efficiency simple instructions sets like arm can live without mop cache but x86 - just need it to maintain decent efficiency. Intel small cores probably fail for efficiency because their lack of mop cache.
 
Last edited:
Reactions: Executor_, lightmanek, Tlh97 and 1 other person
Upvote 0 Downvote

uzzi38

Platinum Member
Oct 16, 2019
2,669
6,202
146
https://twitter.com/x/status/1787789405400289499

@mikk

Come on man, you know platform TOPs is a useless metric - no software will take advantage of CPU, GPU and NPU at the same time. Not even a combination of two of them. Only thing that really matters is the individual parts.

You can argue LNL iGPU hitting higher TOPs is a good thing, but it's functionally useless if the NPU gets the same or better performance at a fraction the power budget.
 
Reactions: lightmanek, Thibsie, Elfear and 9 others
Upvote 0 Downvote

Mahboi

Senior member
Apr 4, 2024
522
836
91
uzzi38 said:
Come on man, you know platform TOPs is a useless metric - no software will take advantage of CPU, GPU and NPU at the same time. Not even a combination of two of them.
Click to expand...
I assumed the goal of AMD with its APUs was to intelligently distribute the workloads?
Isn't getting the NPU and GPU sharing work the long term goal?
 
Upvote 0 Downvote
G

Ghostsonplanets

Senior member
Mar 1, 2024
388
659
96
Mahboi said:
Isn't getting the NPU and GPU sharing work the long term goal?
Click to expand...
In the long term? Maybe. Not something for current generation of devices or short-term. GPU and NPU are very different pieces of silicon with very different programming models and support. And that's true for both Intel and AMD.

Hence why Platform TOPs, as Uzzi said, is a very useless metric. ISV will either be using NPU or GPU, not both.
 
Reactions: Elfear, Det0x, spursindonesia and 5 others
Upvote 0 Downvote
W

Wolverine2349

Member
Oct 9, 2022
183
72
61
Will desktop Arrow Lake or Lunar Lake or whatever its going to be called for LGA 1851 and Z890 platform released later in 2024 for DIY and OEM desktop PCs have all P-cores and e-cores on a single node/Tile?? Or will the e-cores and P cores be split across different tiles and have the cross latency penalty like AMD dual CCD CPUs have?
 
Upvote 0 Downvote
G

gdansk

Platinum Member
Feb 8, 2011
2,212
2,836
136
Ghostsonplanets said:
GPU and NPU ... with very different programming models and support. And that's true for both Intel and AMD.
Click to expand...
Is it though? For OpenVINO, Windows ML, and so on you simply change the execution device and it does the rest. If you're doing inference it isn't hard to use either device (I don't know about using both, however)
 
Upvote 0 Downvote

dullard

Elite Member
May 21, 2001
25,126
3,516
126
Wolverine2349 said:
Will desktop Arrow Lake or Lunar Lake or whatever its going to be called for LGA 1851 and Z890 platform released later in 2024 for DIY and OEM desktop PCs have all P-cores and e-cores on a single node/Tile?? Or will the e-cores and P cores be split across different tiles and have the cross latency penalty like AMD dual CCD CPUs have?
Click to expand...
Arrow Lake will be desktop and mobile. Lunar Lake is to be ultra-low power mobile only (or at least limited to mobile and embedded applications similar to how Meteor Lake is mobile and embedded).

The LGA 1851 motherboards were rumored to be released starting in Q3 2004 (July through Sept 2024). https://wccftech.com/next-gen-amd-7...-lga-1851-socket-motherboards-q3-2024-launch/ That meshes well with unconfirmed rumors of a June Computex announcement by Intel. https://videocardz.com/newz/intels-...n-client-product-showcase-arrow-lake-incoming

Images of Arrow Lake show a separate CPU tile holding the P cores and most of the E cores. However, if it truly does share the same low power island E cores as Meteor Lake in the SOC tile, then those couple of E cores will be on a different tile. https://www.pcgamesn.com/intel/arrow-lake-cpu-picture
 
Upvote 0 Downvote
W

Wolverine2349

Member
Oct 9, 2022
183
72
61
dullard said:
Arrow Lake will be desktop and mobile. Lunar Lake is to be ultra-low power mobile only (or at least limited to mobile and embedded applications similar to how Meteor Lake is mobile and embedded).

The LGA 1851 motherboards were rumored to be released starting in Q3 2004 (July through Sept 2024). https://wccftech.com/next-gen-amd-7...-lga-1851-socket-motherboards-q3-2024-launch/ That meshes well with unconfirmed rumors of a June Computex announcement by Intel. https://videocardz.com/newz/intels-...n-client-product-showcase-arrow-lake-incoming

Images of Arrow Lake show a separate CPU tile holding the P cores and most of the E cores. However, if it truly does share the same low power island E cores as Meteor Lake in the SOC tile, then those couple of E cores will be on a different tile. https://www.pcgamesn.com/intel/arrow-lake-cpu-picture
Click to expand...

SO wait are you saying that Arrow Lake tiles have e-cores and p-cores in same tile or separate?

And Meteor Lake already has P and e-cores in separate tiles?

And is separate tiles bad for latency so would there be a huge latency hit if tasks have to communicate from the 8 P core tile to the 16 e-core tile like AMD dual CCD communication which is bad for gaming? Or are tiles different and no cross latency communication penalty unlike AMD dual CCDs crossing infinity fabric?

Cause I know current 13th and 14th Gen the e-cores are on same ring bus as P cores so little to no latency penalty like Comet Lake had all 10 P cores on same ring unlike AMD where beyond 8 cores it has to cross to other CCD through infinity fabric.
 
Last edited:
Upvote 0 Downvote

dullard

Elite Member
May 21, 2001
25,126
3,516
126
Wolverine2349 said:
SO wait are you saying that Arrow Lake tiles have e-cores and p-cores in same tile or separate?

And Meteor Lake already has P and e-cores in separate tiles?

And is separate tiles bad for latency so would there be a huge latency hit if tasks have to communicate from the 8 P core tile to the 16 e-core tile like AMD dual CCD communication which is bad for gaming? Or are tiles different and no cross latency communication penalty unlike AMD dual CCDs crossing infinity fabric?

Cause I know current 13th and 14th Gen the e-cores are on same ring bus as P cores so little to no latency penalty like Comet Lake had all 10 P cores on same ring unlike AMD where beyond 8 cores it has to cross to other CCD through infinity fabric.
Click to expand...
Both same tile AND separate tile. Meteor Lake has 3 core types: P, E, and low-power island E. The P and E cores are on the same tile. The low-power island E cores are on a different separate tile. That said, properly coded software would be set not to go back and forth to this low-power island (of course not all software is coded very well). See the latencies here where the last two cores are the low-power island E cores with much higher latencies:

I expect similar results with Arrow Lake.

AMD's core-to-core latencies are generally good. I don't know what you are talking about there. Please go to an AMD thread to talk more about them. https://images.anandtech.com/doci/21242/AMD Ryzen 7 8700G Core to Core Latency APU.png
 
Last edited:
Reactions: Tlh97
Upvote 0 Downvote
W

Wolverine2349

Member
Oct 9, 2022
183
72
61
dullard said:
Both same tile AND separate tile. Meteor Lake has 3 core types: P, E, and low-power island E. The P and E cores are on the same tile. The low-power island E cores are on a different separate tile. That said, properly coded software would be set not to go back and forth to this low-power island (of course not all software is coded very well). See the latencies here where the last two cores are the low-power island E cores with much higher latencies:

I expect similar results with Arrow Lake.

AMD's core-to-core latencies are good. I don't know what you are talking about there. Please go to an AMD thread to talk more about them. https://images.anandtech.com/doci/21242/AMD Ryzen 7 8700G Core to
dullard said:
Both same tile AND separate tile. Meteor Lake has 3 core types: P, E, and low-power island E. The P and E cores are on the same tile. The low-power island E cores are on a different separate tile. That said, properly coded software would be set not to go back and forth to this low-power island (of course not all software is coded very well). See the latencies here where the last two cores are the low-power island E cores with much higher latencies:

I expect similar results with Arrow Lake.

AMD's core-to-core latencies are generally good. I don't know what you are talking about there. Please go to an AMD thread to talk more about them. https://images.anandtech.com/doci/21242/AMD Ryzen 7 8700G Core to Core Latency APU.png
Click to expand...


Oh I see what you are saying. It makes sense now. All P and regular e-cores are on same tile. The low power island e-cores are on separate tile and thus there is a latency hit going to them. So Arrow Lake since it's desktop and not mobile will probably not have those low powered island e-cores and regular e-cores instead and thus should be on same tile like Meteor Lake.
Click to expand...

And yes AMD's core to core latency is good if its on the same CCD which 8 core AMD CPUs have. However AMD CPUs above 8 cores have dual CCDs and the latency crossing between CCDs is a big hit. Like the 16 core parts are dual 8 core CCDs: https://www.anandtech.com/show/1758...ryzen-5-7600x-review-retaking-the-high-end/10
 
Upvote 0 Downvote

Gideon

Golden Member
Nov 27, 2007
1,673
3,804
136
Reactions: lightmanek, igor_kavinski, Elfear and 6 others
Upvote 0 Downvote

Thunder 57

Platinum Member
Aug 19, 2007
2,722
3,911
136
DavidC1 said:
No. If anything uop caches will be sharing the fate of Hyperthreading and be axed in the future.

Uop caches are a remnant of the extreme clock focus of Netburst. Rather than thinking it brings more performance, you should think of it as maintaining performance while allowing it to raise clocks.

Raichu and others said 8-way decode for Lion Cove.

Also, for Skymont to be 8-way, it has to be 2x4. Since the cluster approach is to reduce impact of power/area of decoders, it makes no sense as Intel said cluster 3-way minimizes impact of decoders. Raichu might have thought it was 8-way in the beginning, but later clarified that its 3x3-way.
Click to expand...

In what world are uop caches going away? If anything with AMD at least they have been relying on it more, increasing its size nearly every generation. Zen 2 shrunk the L1i cache just to increase the uop cache size. I've read they can be power hungry, but the pros seem to far outweigh the cons.
 
Reactions: Thibsie, igor_kavinski, Tlh97 and 1 other person
Upvote 0 Downvote

cytg111

Lifer
Mar 17, 2008
23,335
12,947
136
I am out of the loop here, could someone tell me if this is a sort of correct assessment: Arrow Lake is Intels comeback chip? Return to cutting edge fabbing and going head to head with TSMC?
 
Upvote 0 Downvote
I

igor_kavinski

Lifer
Jul 27, 2020
16,822
10,768
106
cytg111 said:
Return to cutting edge fabbing and going head to head with TSMC?
Click to expand...
Even Intel themselves said they won't be able to regain manufacturing process leadership before 2026. And since this is Intel we are talking about, that's 11:57 P.M. on 31st December, 2026 when Intel sends out the press release announcing that they have successfully regained leadership with the most advanced manufacturing process in the entire frickin' Universe. With a test chip.

Yes. A frickin' beautiful test chip.

HVM? Your guess is as good as mine.
 
Reactions: mavere, Tlh97, spursindonesia and 3 others
Upvote 0 Downvote

cytg111

Lifer
Mar 17, 2008
23,335
12,947
136
DrMrLordX said:
No, not really. Some Arrow Lake chips will be fabbed on TSMC N3B. If you can believe it.
Click to expand...
Damn, thought Arrow Lake was going to be delivered with cutting edge fabbing tech, backside power delivery and whatnot... Guess the beautiful lady here is either misinformed or doing a balancing act.


edit : No actually she says that the real pivotal moment will be 14an in 2027 for intel, make it or break it.
Anyway I think I am taking that bet and be buying up some INTC the coming time.
 
Last edited:
Reactions: Thibsie
Upvote -1 Downvote

Hulk

Diamond Member
Oct 9, 1999
4,269
2,089
136
Since ASML makes all of the machinery to mass produce these chip patterns if a couple of companies each have the latest and greatest how is anyone in the lead? Or is the machinery only half the battle and the rest is knowing how to use it?
 
Reactions: scannall
Upvote 0 Downvote
D

DavidC1

Senior member
Dec 29, 2023
203
284
96
Thunder 57 said:
In what world are uop caches going away? If anything with AMD at least they have been relying on it more, increasing its size nearly every generation. Zen 2 shrunk the L1i cache just to increase the uop cache size. I've read they can be power hungry, but the pros seem to far outweigh the cons.
Click to expand...
Hyperthreading/SMT was once thought by every engineer to be something that was required to have but now it's not far away from being relegated to niches that VLIW architectures occupy.

Just because an alternative hasn't been thought of doesn't mean it will remain that way forever.
cytg111 said:
edit : No actually she says that the real pivotal moment will be 14an in 2027 for intel, make it or break it.
Anyway I think I am taking that bet and be buying up some INTC the coming time.
Click to expand...
What is the proportion of the reasons you are watching the channel? Because she has visually appealing features or that she offers information that pertains to your bias?

When it comes to gigantic scale mass manufacturing such as modern semiconductors, being out there in the real world with scale is king. They weren't able to get 10nm out in any capacity until they decided to do a little with Cannonlake and very quickly they were able to ramp 10nm to yields. Intel may take the lead but it'll take extraordinary measures to do so and perhaps TSMC messing up. They may take the lead but that's still hope more than anything.
 
Last edited:
Upvote 0 Downvote
D

DavidC1

Senior member
Dec 29, 2023
203
284
96
igor_kavinski said:
Even Intel themselves said they won't be able to regain manufacturing process leadership before 2026. And since this is Intel we are talking about, that's 11:57 P.M. on 31st December, 2026 when Intel sends out the press release announcing that they have successfully regained leadership with the most advanced manufacturing process in the entire frickin' Universe. With a test chip.
Click to expand...
It is actually supposed to be sometime in 2025 with Darkmont-based Clearwater Forest.

By then it will become clear whether Gelsinger was talking out of his behind or he is the real deal. 18A is the end of 5N4Y promise. After that they go back to 2 year cadence.
 
Reactions: spursindonesia
Upvote 0 Downvote
You must log in or register to reply here.

TRENDING THREADS

COMPANY
RESOURCES
FOLLOW
Top Bottom
sale-70-410-exam    | Exam-200-125-pdf    | we-sale-70-410-exam    | hot-sale-70-410-exam    | Latest-exam-700-603-Dumps    | Dumps-98-363-exams-date    | Certs-200-125-date    | Dumps-300-075-exams-date    | hot-sale-book-C8010-726-book    | Hot-Sale-200-310-Exam    | Exam-Description-200-310-dumps?    | hot-sale-book-200-125-book    | Latest-Updated-300-209-Exam    | Dumps-210-260-exams-date    | Download-200-125-Exam-PDF    | Exam-Description-300-101-dumps    | Certs-300-101-date    | Hot-Sale-300-075-Exam    | Latest-exam-200-125-Dumps    | Exam-Description-200-125-dumps    | Latest-Updated-300-075-Exam    | hot-sale-book-210-260-book    | Dumps-200-901-exams-date    | Certs-200-901-date    | Latest-exam-1Z0-062-Dumps    | Hot-Sale-1Z0-062-Exam    | Certs-CSSLP-date    | 100%-Pass-70-383-Exams    | Latest-JN0-360-real-exam-questions    | 100%-Pass-4A0-100-Real-Exam-Questions    | Dumps-300-135-exams-date    | Passed-200-105-Tech-Exams    | Latest-Updated-200-310-Exam    | Download-300-070-Exam-PDF    | Hot-Sale-JN0-360-Exam    | 100%-Pass-JN0-360-Exams    | 100%-Pass-JN0-360-Real-Exam-Questions    | Dumps-JN0-360-exams-date    | Exam-Description-1Z0-876-dumps    | Latest-exam-1Z0-876-Dumps    | Dumps-HPE0-Y53-exams-date    | 2017-Latest-HPE0-Y53-Exam    | 100%-Pass-HPE0-Y53-Real-Exam-Questions    | Pass-4A0-100-Exam    | Latest-4A0-100-Questions    | Dumps-98-365-exams-date    | 2017-Latest-98-365-Exam    | 100%-Pass-VCS-254-Exams    | 2017-Latest-VCS-273-Exam    | Dumps-200-355-exams-date    | 2017-Latest-300-320-Exam    | Pass-300-101-Exam    | 100%-Pass-300-115-Exams    |
http://www.portvapes.co.uk/    | http://www.portvapes.co.uk/    |