Is Apple preventing you from running Windows? How, exactly?
I don't use Apple's stuff, and I'm not the target market for it - but Apple has done absolutely nothing to stop Microsoft from supporting their hardware, as far as I'm aware. Also, the Win/ARM virtualization story on ARM MacOS is, from...
Afaik Snapdragons enable no SVE, for reasons that are not immediately obvious to me (but variable-length vector machines are a little more of a pain to work with than commonly believed, IME.) I don't think SME even exists in the licensable cores right now.
Lot of extremes in this thread and elsewhere - either M4 is the most amazing thing ever or doomed Apple.
It seems to me like the truth is somewhere in the middle - that the M4 is a decent rev of the M3 architecture with some nice freebies (SME, two additional small cores) and a small clock bump...
Probably a inevitable issue, though - new extensions are added by vendors all the time. I'm not sure what the solution is. SPEC doesn't prohibit submission with whatever ops the user wants, but vendor SPEC submissions are also kinda worthless.
Perhaps, if Geekbench is wedded to the model of...
I put together a quick and dirty clock-normalized comparison spreadsheet between M4 and A17:
I'm using https://browser.geekbench.com/v6/cpu/6010114 for the iPhone data. (Also it only just occurred to me that I could have compared against M3 instead of A17. I am a very stupid lady at times...
I only looked at it briefly, but I think a lot of the gains are SME. The clock-normalized gains for the normal integer-spaghetti subtests against A17 are pretty small, often close to flat.
The benchmark is Affinity Photo's internal bench, which AFAIK is MT.
I'm actually kind of impressed with +50% if it's demonstrated across a reasonably wide set of multithreaded workloads. I don't think that's a bad bump across two gens.
There's also fusion to consider. As you know, "width" is kind of a fuzzy concept, especially with aggressively OoO machines where number of uops executing in a given cycle can greatly exceed the machine's sustained whole-pipe width.
Note that Neoverse V2, which is emphatically an 8-wide core...
Seems like a solid number if it's actually at 2.1GHz, but also like there's a lot of murkiness around it. (Also, isn't it a bit early to be seeing X5 numbers? IIRC final RTL ships only a short while before ARM's annual announcement, no?)
Yeah, Loongarch is the current ISA of Loongson - it looks like a de-legacied MIPS without a lot of the nastiness (delayed braches, hi/lo); from what I've seen it's not a bad ISA design. There are available manuals. The current-gen Loongson, which uses it, is also a very reasonable...
Do you know if there are any docs available? I looked it up and only saw stuff from what seemed like very dubious blogs and "news" sites. One claimed it was a VLIW (and also insisted this was somehow revolutionary.)
Yep. We'll know in weeks.
I don't think we'd be seeing the level of OEM interest that we are if the situation were as bad as some here seem to believe, though. Certainly OEMs were not lining up to ship premium Kaveri or Richland devices. I also freely admit that I have no experience directly...
Charlie says a lot of things. Release is close enough that it will soon become very clear whether they're true or not. Considering he repeatedly refers to the X Plus as the "X Pro", I'm frankly questioning some of his attention to detail on this one.
IBM may have patented some implementation details, but the concept has been done before by others - TileGX, for instance, had a "virtual L3" consisting of foreign L2 slices.
The revolution that was hyped up was more for the Elite, FWIW, and performance for that part continues to look very solid. The Plus is a deliberately nuked midrange model. With that in mind, is "matches an upper-midrange AMD part's ST and beats it at MT" really so bad? It's certainly a more...
I mean, it's still a solid improvement over 8cx Gen 3 and competitive with the x86 midrange. The targeted Geekbench numbers seem to exceed the 7640U by a solid margin, for instance.
Combine that with internal political feuds on a scale that makes IBM look mild. (I don't know if this is necessarily still the case, but it certainly used to be, and I've seen nothing to suggest that it's changed.)
Have you seen any deets yet about what HarmonyOS Next actually is? It seemed like there were strong hints they were going to be building it around their LiteOS RTOS kernel (which I conceptually approve of) but very few details.
One flavor of custom core AFAIK, at least in the 9000S. To the best of my knowledge it's 1+3 custom cores in two different configurations, and 4 Cortex-A510. But the core IDs being different is evidence I may be wrong. (Re: the 9010 specifically, I guess one possibility is that the 9010's big...
13-wide, no? The optimization guide seems to suggest such.
It's also fully 64b now and has an MMU. Theoretically TI could support full-fat Linux on it, though I doubt they will.
(And yeah, it's probably off topic and I don't want to derail further - was doing definition on a board design last...
Or they've improved their DVFS curve as development continued. I don't think I'd conclude they're hiding something based on this - but, as always, assume that pre-release vendor claims are under the most favorable circumstances possible.
TI C7000 - it's a 13-wide VLIW that looks kind of like one of the two slices of the C6000 with a large vector block on the side. Total of four scalar execution pipes, six vector pipes, and three shared (one branch and two load/store, with some limits on vector+vector load/store ops.) Some...
Geekerwan's SPEC results, if I recall, also showed large MT gains - but this could also be a case of the benchmark and/or the VM it runs on being improperly pinned to one core, I figure.
You're right, of course. My apologies. I was needlessly confrontational. I'm underslept and having a bit of a rough week, but that's no excuse.
This is the best I've found.
In general, the characteristics of the core line up pretty well with what was roadmapped for Kunpeng 930 - notably SVE...
I don't know why we're rehashing this six months after 9000S's release. It's been well-known to be Taishan (specifically Taishan V120), not an ARM Ltd IP. Huawei has stated so outright and there's the little matter of it having SMT, which pretty categorically excludes A78's.
But sure. You do...
Except it clearly isn't, in this case. The large cores in Kirin 9000S and variants are the Taishan cores built for the Kunpeng 930. (I'm pretty sure we already went over this when the 9000S came out, but I may be mixing it up with conversations I had elsewhere.)
It's just an ID collision.
I have "only" one Itanium system at this point, an rx2800 i4 (final generation HP rack system.)
Highest core count CPU is a TileGX that's been gathering dust for a few years.
Considering the large spectrum of ARM SoC's available and in development, that sounds like a lot. Would you advocate for only one x86 thread?
(Also, can we have a permanent Itanium thread? Please? For me?)
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