Anyone else find it funny that we're already seeing pre-orders for Milan-X EPYC but nothing for Vermeer-X?
Just a speculation, but I think AMD may be taking a hard turn to Milan-X.
That is possible. It sort of depends on how many of the B2-stepping dice are flexible enough to bin for either Vermeer-X or Milan-X. Vermeer-X isn't going to make them anywhere near as much money as Milan-X.
If Raphael is indeed going to be announced/launched at CES, AMD doesn't have long to wait before burying Alder Lake and Raptor Lake in one shot (like they even care; Vermeer is surprisingly competitive with Alder Lake as it is).
Regarding b2 clocks, attributed to either stepping or just another extra year of process maturity, it'll depend more on what clocks the top stacked cache part will have. If the 6950x3d can hit 5 or 4.9ghz still then that'll be the limit and you can probably drop the rest of the line in increments from there. It's a tragedy if the halo part has to drop clocks.I think the B2 stepping will improve the binning a little bit, say just 100 MHz, then the binning at clock speed AMD has been offering becomes almost a non issue.
*redacted*
I think Raphael may at best be teased, officially put on road map (after it disappeared from it).
Also will raphael have a stacked cache option on or very close to launch?
Regarding b2 clocks, attributed to either stepping or just another extra year of process maturity, it'll depend more on what clocks the top stacked cache part will have. If the 6950x3d can hit 5 or 4.9ghz still then that'll be the limit and you can probably drop the rest of the line in increments from there. It's a tragedy if the halo part has to drop clocks.
Another question is will the non stacked parts have the same or slightly reduced peak turbos.
Not that I think it matters too much, the all core clock speeds will be more telling, could non-stacked parts could have a higher sustained all core for example.
Regardless raphael is in a troublesome spot. It's biggest competition is going to be vermeer-x so revealing it too early would be damaging to their product cycle, no matter how much people like us are craving for any informtion.
Also will raphael have a stacked cache option on or very close to launch? Without 3d cache it might not fully outperform vermeer-x. There are only questions for raph and keeping it all under wraps is the best option for now.
Doesn't sound like it. Depending on when Zen 5 launches it could be a mid cycle refresh.
Well, there is a good reason for that. Without V-Cache, on a cache miss, the core is idle at high clock speed, doing nothing, keeping cool, but with V-Cache, there will be fewer cache misses, so core doing more work, generating more heat.
edit2: why not 6nm, because TSMC 6nm doesn't support V-cache...
Well it increases the wafer production capacity with 20% for TSMC (hence the push) and on top of that customers have about 15% more dies per wafer, so APUs on 6nm is an easy choice.Kind of a head-scratcher since TSMC is mostly pushing their N7 customers on to N6 where possible. But Vermeer/Milan will stay N7, even with stacked cache.
Well it increases the wafer production capacity with 20% for TSMC (hence the push) and on top of that customers have about 15% more dies per wafer, so APUs on 6nm is an easy choice.
Well, there is a good reason for that. Without V-Cache, on a cache miss, the core is idle at high clock speed, doing nothing. . . .
I haven't seen it as 'Not supported' but the half nodes are missing if they list it 3, 5, 7.Makes sense, hence my confusion about all Vermeer products staying on N7. And where did you hear that N6 didn't support stacked cache?
I haven't seen it as 'Not supported' but the half nodes are missing if they list it 3, 5, 7.
Could be carelessness or correct that half nodes don't support stacking.
Yes but the thing is that it is also shrinking and for stacking size is important hence extra work that needs to be done again so they may have decided to skip that part. (certainly since the amount of stacking request is limited for now)TSMC considers nodes like N6 and N4 (which are NOT true half nodes) to be optimizations of N7 and N5, respectively. So it is quite possible that support for stacking on N7 means it will also support N6.
It's still running and just inserting NOPs because it doesn't know at the time how long it will need to stall because it can't know how bad the cache miss is until it's worked it's way through to that point.
NOPs are actual instructions and although they were designed to do no operation, they do take up space and used to have the effect of incrementing the instruction pointer.
Maybe it's architecture dependent, but I don't think you'd want to advance the program counter on a NOP, at least not in every case. Even in a simple pipeline there are plenty of cases where it can't advance just due to physical limitations. Anything with OOE an an actual program running probably has something else in the instruction queue that can be executed, but if you've got a simple program that's specifically designed to benchmark certain kinds of performance or better understand those characteristics of the chip it might not have that.
Suppose we've got some program written and specifically designed to test out cache performance in the CPU. Even the fastest caches are still usually at least 3 clock cycles which means that the next operation needs to be delayed until that data becomes available (wether that means being written to the register file or forwarded in some manner) so the processor needs some mechanism to stall on a specific instruction until it can actually execute it with the correct data.
The shrink only occurs on the New Tapeout side. The Re-Tapeout side, has no shrink and gets the benefit of SAQP 193i to Single-Patterned EUV.Yes but the thing is that it is also shrinking and for stacking size is important hence extra work that needs to be done again so they may have decided to skip that part. (certainly since the amount of stacking request is limited for now)