Info 64MB V-Cache on 5XXX Zen3 Average +15% in Games

[Kedas]

Well we know now how they will bridge the long wait to Zen4 on AM5 Q4 2022.
Production start for V-cache is end this year so too early for Zen4 so this is certainly coming to AM4.
+15% Lisa said is "like an entire architectural generation"

 

[DrMrLordX]

I think that falls into the "like custom purposefully bad code hard" category to stall it.

Like 3DPM v1?

. . .

(lol)

Some new B2/A0 stepping SKUs incoming?

Wait. A0? What would that be?

 

[SteinFG]

Wait. A0? What would that be?

There's 6 SKUs and no USB4 on the A0 product page, so it's probably Barcelo"U": 3 non-pro SKUs (R3, R5, R7), and 3 pro SKUs (R3, R5, R7)
Also lines up with Barcelo being A0 since there're probably no changes done compared to Cezanne

 

[Kedas]

About 6nm or in between full nodes supporting stacking or not:

I see that the press release of N4P does mention an 6% density increase but no mention of 3Dfabric.
Then 7 weeks later the press release of N4X, it does mention 3DFabric but no mention of a density increase.
If there is no density increase for N4X compared to N5 then 3DFabric would just be a copy past from N5.

So I still think it's very likely that N6 does not do 3DFabric and neither does N4P.

 

[Joe NYC]

On an OOP processor, the core is never idle. It may push latency into some sequences, but you would have to work hard, like custom purposefully bad code hard to make a stall that long with such large register file (zen 168).

Even with OOP and SMT, cache still helps, which means, CPU does not have enough to do on cache miss.

Since cache helps performance, more work gets done in the same time, without cache, the CPU is just idling at high speed part of that time.

 

[Joe NYC]

edit: nevermind here it is: https://min.news/en/tech/b43fdca64913b7776ea173b95ec971fa.html

Good catch.

edit2: why not 6nm, because TSMC 6nm doesn't support V-cache...

Is that something official? Or speculation?

 

[Joe NYC]

Wait. A0? What would that be?

Rembrandt?

 

[Schmide]

Even with OOP and SMT, cache still helps, which means, CPU does not have enough to do on cache miss.

Since cache helps performance, more work gets done in the same time, without cache, the CPU is just idling at high speed part of that time.

Stop thinking linearly. A cache miss is only going to insert ~60 latency into chains that may span 100s of clocks. The CPU is never idle. Moreover, when a cache miss to main memory happens, a new way must be loaded forcing an existing way down the hierarchy. L3 is a victim cache. On top of that you have the AGU always scheduling the next datum.

I guess it may be doing less but it is far from idle.

 

[Kedas]

Is that something official? Or speculation?

If tomorrow AMD doesn't mention any future product on 6nm with stacking then you can take it as official since there isn't any important TSMC customer using 6nm stacking. (While there are already a few official sackings on 5nm)
(Marketing people never mention what it can't do only what it can.)

It's a bit proving that it doesn't exist....

 

[igor_kavinski]

Speaking of tomorrow, what are the predictions of the various armchair analysts here?

My optimistic predictions:
Zen3D available for sale by end of January
New SKU 5990X (24C/48T OR 20C/40T) with V-cache (AMD would love to price this at $999)
Radeon 7000 series performance teaser
Zen 4 with DDR5 25% IPC improvement over Zen 3 with DDR4
Persistent memory for Epyc servers

 

[maddie]

Speaking of tomorrow, what are the predictions of the various armchair analysts here?

My optimistic predictions:
Zen3D available for sale by end of January
New SKU 5990X (24C/48T OR 20C/40T) with V-cache (AMD would love to price this at $999)
Radeon 7000 series performance teaser
Zen 4 with DDR5 25% IPC improvement over Zen 3 with DDR4
Persistent memory for Epyc servers

Politely, isn't this CES?

 

[igor_kavinski]

Politely, isn't this CES?

Yes, the AMD event.

 

[Thunder 57]

Speaking of tomorrow, what are the predictions of the various armchair analysts here?

My optimistic predictions:
Zen3D available for sale by end of January
New SKU 5990X (24C/48T OR 20C/40T) with V-cache (AMD would love to price this at $999)
Radeon 7000 series performance teaser
Zen 4 with DDR5 25% IPC improvement over Zen 3 with DDR4
Persistent memory for Epyc servers

I'd love it if we got half as much info. No way they will add a high core SKU at this point. Don't think it's practical or even physically possible on AM4.

Don't think we'll hear anything about Epyc. I'd bet they say Q1 for Zen3D but hopefully you're right. I could see them touch on Radeon 7000 too. Don't think well get much on Zen 4 to avoid Osborne effect.

 

[Det0x]

Seems like intel are running scared
*edit*
Already posted in other thread

https://twitter.com/x/status/1478079758898446337

Intel Core i9-12900KS up to 5.5 GHz boost clock?

The company has just posted a mysterious picture on its social media, claiming that the 12th Gen Core (Alder Lake) CPUs are already topping the ‘best CPU’ lists and are already available. However, this is not the final word, as Intel teases ‘a next stop’ at 5.5 GHz.

In other words, this might be the first tease of the upcoming factory binned chip which we mentioned last month. The company is working on a Core i9-12900KS CPU with all Performance-core boost frequency at 5.2 GHz. This is exactly what we said in our article and this is exactly what the HWINFO screenshot posted by Intel appears to show.

Furthermore, we learn that the highest boost clock of the 12900KS would be 5.5 GHz, which is a single-core frequency. Overall, this should be the fastest Alder Lake-S CPU that will be set to compete against the upcoming AMD Ryzen 6000 CPU series with 3D V-Cache.

 

[Thunder 57]

Seems like intel are running scared
*edit*
Already posted in other thread

https://twitter.com/x/status/1478079758898446337

https://videocardz.com/newz/intel-teases-core-i9-12900ks-cpu-with-boost-clock-up-to-5-5-ghz

Will they have chilled water under the demo unit?

 

[Mopetar]

That's the beauty of out of order execution. It's just a bunch of queues and mapped registers. The load store unit need only move data in and out of the register file. When the data makes it there, it is sent down a pipeline to be worked on.

I guess the point I was making is that even in absence of any instruction to work on at some stage in a pipeline, that hardware is still producing values (the logic gates are still operating on some values and producing some output and transistors are potentially switching) but they don't represent anything and won't be used for any actual results.

The hardware doesn't idle while waiting on cache, but it doesn't matter what it's doing as long as those results aren't being written to registers, cache, etc.

So lets put this in context. We're talking about the difference in stalling a huge 32 MiB vs 96 MiB L3 multi way victim cache. So a span operation greater than 32 MiB 16 way. I think that falls into the "like custom purposefully bad code hard" category to stall it.

I mean it's purposely bad in the sense that it allows us to understand performance characteristics. Hooking up a giant weight to a pickup truck is purposefully bad since that doesn't represent actual work that people are buying the truck for, but it will help determine the towing capabilities of the vehicle.

Sure you could just go out and buy some boats, trailers, etc. that people tow all the time much like you can just run some actual software job, and while that may be more realistic or representative of actual work, it isn't always as enlightening from a technical or academic perspective.

 

[jpiniero]

Speaking of tomorrow, what are the predictions of the various armchair analysts here?

My optimistic predictions:
Zen3D available for sale by end of January

Gotta say I'd think there would be more leaks if this was actually being released in January.

 

[Saylick]

Speaking of tomorrow, what are the predictions of the various armchair analysts here?

Sure, I'll throw my hat into the ring:
- Zen 3D soft launch, with models available for retail in early February.
- Rembrandt unveil, soft launch, with models available by end of January.
- Zen 4 teaser, no hard numbers or IPC gains, but likely performance targets using the "greater than" symbol and stating that they are still tuning the performance (e.g. >25% performance over Zen 3 across a wide-range of work-loads). Maybe highlight or re-iterate the features of the platform, e.g. Zen 4 on N5 HPC, DDR5 support, AM5 socket, PCIe 5 support, etc.
- No RDNA 3 teaser.
- Radeon RX 6500XT soft launch.
- Radeon RX 6850 mobile dGPU soft launch.

 

[eek2121]

Sure, I'll throw my hat into the ring:
- Zen 3D soft launch, with models available for retail in early February.
- Rembrandt unveil, soft launch, with models available by end of January.
- Zen 4 teaser, no hard numbers or IPC gains, but likely performance targets using the "greater than" symbol and stating that they are still tuning the performance (e.g. >25% performance over Zen 3 across a wide-range of work-loads). Maybe highlight or re-iterate the features of the platform, e.g. Zen 4 on N5 HPC, DDR5 support, AM5 socket, PCIe 5 support, etc.
- No RDNA 3 teaser.
- Radeon RX 6500XT soft launch.
- Radeon RX 6850 mobile dGPU soft launch.

I can mostly get behind that, except the RX 6500 XT launch appears to be relatively close.

 

[eek2121]

Will they have chilled water under the demo unit?

Jokes aside, that is for single core performance. Power consumption has never really been much of an issue for single core boost. Depending on how well GC scales with frequency, that chip might show some considerable gains for single core workloads.

 

[Joe NYC]

If tomorrow AMD doesn't mention any future product on 6nm with stacking then you can take it as official since there isn't any important TSMC customer using 6nm stacking. (While there are already a few official sackings on 5nm)
(Marketing people never mention what it can't do only what it can.)

It's a bit proving that it doesn't exist....

It would not be an exhaustive proof, but another hint.

I think that beyond the base Zen 3 CCD die, AMD does not have any other suitable candidates for stacking.

Here is another point to support your side of the argument:

Nave 31 and Navi 32 are going to be on N5 and will have stacking (of infinity cache, based on the leaks)
Navi 33 will be on N6 and will not have stacking of Infinity Cache.

But still, I would like to hear official statement on this from TSMC.

 

[Hans Gruber]

The Intel i5 12400 is due to be released this month. The chip is 6 core 12 thread (golden cove cores). No gracemont cores (weak cores). They say it outperforms the 5600x. Some say it will sell between $150-$180. I think this would mean Zen3D chips would need to hit the market sooner rather than later. AMD needs that 15% gaming boost.

 

[DrMrLordX]

Zen3D available for sale by end of January

I've heard early February. See below.

New SKU 5990X (24C/48T OR 20C/40T) with V-cache (AMD would love to price this at $999)

On AM4? No. Also see below.

No way they will add a high core SKU at this point. Don't think it's practical or even physically possible on AM4.

Agreed, 24c won't cut it on AM4. With 170W power limits being discussed for AM5, it's possible on that platform . . . maybe.

- Zen 3D soft launch, with models available for retail in early February.

At least one leaker has mentioned that possibility. Seems probable.

The Intel i5 12400 is due to be released this month. The chip is 6 core 12 thread (golden cove cores). No gracemont cores (weak cores). They say it outperforms the 5600x. Some say it will sell between $150-$180. I think this would mean Zen3D chips would need to hit the market sooner rather than later. AMD needs that 15% gaming boost.

What makes you think AMD will be selling a 6c Vermeer-X/Zen3d?

 

[jamescox]

Seems like intel are running scared
*edit*
Already posted in other thread

https://twitter.com/x/status/1478079758898446337

https://videocardz.com/newz/intel-teases-core-i9-12900ks-cpu-with-boost-clock-up-to-5-5-ghz

That is good news if true. Not because “OMG 5.5 GHz”, but because this would imply that Intel thinks they need a response to whatever AMD is launching and that response is essentially an even more overclocked and/or cherry picked part. This makes me think that AMD’s X3D parts and/or the APU parts are going to perform very well, well enough that current intel parts are not going to look very competitive.

 

[Mopetar]

The Intel i5 12400 is due to be released this month. The chip is 6 core 12 thread (golden cove cores). No gracemont cores (weak cores). They say it outperforms the 5600x. Some say it will sell between $150-$180. I think this would mean Zen3D chips would need to hit the market sooner rather than later. AMD needs that 15% gaming boost.

I doubt AMD is going to waste stacked dies on a 5600-level part. Really they can just cut the price if they need to, which considering that Zen 3 has been on the market for over a year now and the $50 premium that AMD added to most of the lineup, it's hard to argue that a price cut isn't in order.

Right now AMD doesn't even have anything from their latest generation in that price bracket. Even the older Zen 2 CPUs that originally released in that price range are being listed for above MSRP. The Ryzen 3100 is listed for $199 on Amazon. It's only $149 on Newegg, but out of stock there. So either Intel has enough supply to handle the crazy market demand or they're leaving a lot of money on the table pricing it below $200.

 

[Saylick]

At least one leaker has mentioned that possibility. Seems probable.

Hahaha, okay, you've rumbled my game. My list wasn't really my expectations but more like a compilation of what I thought was credible from the rumor mill in the last 6 months.