There is a bunch of different stacking tech, but I don’t think I have seen any tech where they polish down a chip for TSVs after dicing. There are a bunch of new packaging technologies that involve packaging steps applied at the wafer stage. They have chip on wafer (CoW) and wafer on wafer (WoW). WoW means they stack multiple wafer, bond them, and then dice. This might be used for something like HBM stacks. They would polish down the whole wafer, which is floppy like a piece of paper at the thicknesses required, apply micro-solder balls, stack multiple such wafers, bond, and then dice into die stacks. I haven’t researched the specifics that much, but I believe the X3D die are a CoW tech. I might be mixing some things up; there is a lot of new packaging tech. The cpu wafer would need to be polished down to something like 20 microns thickness from something like 700. I don’t think that would be possible or really doable for individual die at ~80 mm2. I assume that they dice the cache die wafer and place the chips on a carrier wafer (sometimes called a reconstituted wafer) with filler silicon also. They then bond the layers and dice the combined wafer. In this case there is no binning of cpu die before stacking. It may not be possible to test cache die either, even though they are diced. The cache die will have some built in redundancy, so the yield on cache is likely very high.