Discussion Apple Silicon SoC thread

[Eug]

M1
5 nm
Unified memory architecture - LP-DDR4
16 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 12 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache
(Apple claims the 4 high-effiency cores alone perform like a dual-core Intel MacBook Air)

8-core iGPU (but there is a 7-core variant, likely with one inactive core)
128 execution units
Up to 24576 concurrent threads
2.6 Teraflops
82 Gigatexels/s
41 gigapixels/s

16-core neural engine
Secure Enclave
USB 4

Products:
$999 ($899 edu) 13" MacBook Air (fanless) - 18 hour video playback battery life
$699 Mac mini (with fan)
$1299 ($1199 edu) 13" MacBook Pro (with fan) - 20 hour video playback battery life

Memory options 8 GB and 16 GB. No 32 GB option (unless you go Intel).

It should be noted that the M1 chip in these three Macs is the same (aside from GPU core number). Basically, Apple is taking the same approach which these chips as they do the iPhones and iPads. Just one SKU (excluding the X variants), which is the same across all iDevices (aside from maybe slight clock speed differences occasionally).

EDIT:



M1 Pro 8-core CPU (6+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 16-core GPU
M1 Max 10-core CPU (8+2), 24-core GPU
M1 Max 10-core CPU (8+2), 32-core GPU

M1 Pro and M1 Max discussion here:

Page 78 - Discussion - Apple Silicon SoC thread

Page 78 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

M1 Ultra discussion here:

Page 109 - Discussion - Apple Silicon SoC thread

Page 109 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

M2 discussion here:

Page 127 - Discussion - Apple Silicon SoC thread

Page 127 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

Second Generation 5 nm
Unified memory architecture - LPDDR5, up to 24 GB and 100 GB/s
20 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 16 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache

10-core iGPU (but there is an 8-core variant)
3.6 Teraflops

16-core neural engine
Secure Enclave
USB 4

Hardware acceleration for 8K h.264, h.264, ProRes

M3 Family discussion here:

Page 215 - Discussion - Apple Silicon SoC thread

Page 215 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

M4 Family discussion here:

Page 263 - Discussion - Apple Silicon SoC thread

Page 263 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

 

[repoman27]

What’s the size of the base M3 die?

I summarized the die size estimates for the various M series chips here:

Page 259 - Discussion - Apple Silicon SoC thread

Page 259 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

M3 is supposed to be around 146-ish mm2 on N3B. >140 anyway. That could suggest a hypothetical M3 on N3E might be over 150 mm2.

My initial estimates based on the die images provided by Apple and measurements of IP blocks shared with the A17 Pro were as follows:

M3: 12.64 mm x 10.67 mm = 135 mm²
M3 Pro: 12.69 mm x 14.96 mm = 190 mm²
M3 Max: 20.40 mm x 21.03 mm = 429 mm²

I'm pretty sure these are a lot closer than the ones Eug sourced, but they are still based on A17 Pro measurements provided by Revegnus (@Tech_Reve). I haven't had the opportunity to verify them yet though.

 

[Eug]

My initial estimates based on the die images provided by Apple and measurements of IP blocks shared with the A17 Pro were as follows:

M3: 12.64 mm x 10.67 mm = 135 mm²
M3 Pro: 12.69 mm x 14.96 mm = 190 mm²
M3 Max: 20.40 mm x 21.03 mm = 429 mm²

I'm pretty sure these are a lot closer than the ones Eug sourced, but they are still based on A17 Pro measurements provided by Revegnus (@Tech_Reve). I haven't had the opportunity to verify them yet though.

I didn't do any calculations myself, but FWIW, the 146 number was published by Tom's Hardware, referencing a tweet from @Frederic_Orange who counted 415 M3 dies for a 3 nm wafer:

Apple Spent $1 Billion to Tape Out New M3 Processors: Analyst

Very few companies can afford a platform like Apple's M3.

www.tomshardware.com

https://twitter.com/x/status/1719753967683383594

Perhaps going about it this way overestimates the size, but I did not attempt to work out the math, since I wouldn't know how to calculate the unused area of the wafer.

Anyhow, if it truly is 135 mm2 on N3B, then that could put a hypothetical N3E version of M3 at well over 140 mm2. I personally won't attempt to guess the size of an M4 on N3E.

 

[Eug]

I don't know how accurate this would be, but knowing that the width of the chip is roughly 18-20% wider than the height, I plugged some numbers into this die per wafer calculator, using the default settings for the last 3 variables:

13.22 x 11.11 mm = 146.87 mm2 = 415 dies

 

[SpudLobby]

What’s the size of the base M3 die?

146mm^2 lololol.


So the same thing.

Edit: or 135. Whatever. It’s the same and it’s gonna be funny because it’ll show all the node whiners that it doesn’t do everything. Very much doubt Intel is going to pull a 3150 GB6 ST under 10W, and we already know the GPU is more M1-class on power and M2 on perf at peak (well slightly higher with more power) by their own documents.

It will be a good part because they’ll fix some idle stuff relative to current Intel parts and likewise Lion Cove and Skymont will be big upgrades and on a new node, but again, directional movement getting them to good enough I think is the best way to see it. I might even buy it.

But I don’t think it seems impressive from an engineering POV at all by any accounts, it’s more like Intel showing up to class halfway through. A very late catchup with more $ spent on it.

 

[Tigerick]

I summarized the die size estimates for the various M series chips here:

Page 259 - Discussion - Apple Silicon SoC thread

Page 259 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

M3 is supposed to be around 146-ish mm2 on N3B. >140 anyway. That could suggest a hypothetical M3 on N3E might be over 150 mm2.

Eug, you do know the advantage of N3B process. Have you ever thought about what Apple going to upgrade the upcoming M4 SoC?

I am expecting 2 more e-cores, 2 more GPU cores and SLC cache expansion. Not to mention the upgrades of NPU TOPS. Why does Apple switching to different design and lower density process for Mac lineup? I am sure Apple will put in more than 100 billion transistors in upcoming M4 Max. That's why I believe Apple will maintain the same process for upcoming M4 lineup...And that's what Mark Gurman claimed as well

 

[Eug]

Eug, you do know the advantage of N3B process. Have you ever thought about what Apple going to upgrade the upcoming M4 SoC?

I am expecting 2 more e-cores, 2 more GPU cores and SLC cache expansion. Not to mention the upgrades of NPU TOPS. Why does Apple switching to different design and lower density process for Mac lineup? I am sure Apple will put in more than 100 billion transistors in upcoming M4 Max. That's why I believe Apple will maintain the same process for upcoming M4 lineup...And that's what Mark Gurman claimed as well

? Are you suggesting the next chip series will also be N3B? If so, you're pretty much the only person that believes this, and no, Mark Gurman didn't claim this.

 

[Tigerick]

? Are you suggesting the next chip series will also be N3B? If so, you're pretty much the only person that believes this, and no, Mark Gurman didn't claim this.

You should check the leaks by Mark Gurman

The M4 chips will be built on the same 3-nanometer process as the M3 chips, but Apple supplier TSMC will likely use an improved version of the 3nm process for boosts in performance and power efficiency

 

[Eug]

You should check the leaks by Mark Gurman

--

The M4 chips will be built on the same 3-nanometer process as the M3 chips, but Apple supplier TSMC will likely use an improved version of the 3nm process for boosts in performance and power efficiency

I think you are misunderstanding that sentence. N3B and N3E are both N3 "3 nm", but N3E is an improved version of the 3 nm process for boosts in performance and/or power efficiency. According to the analysts and the experts here, N3B is essentially dead soon.

In fact, that's probably partially the reason there was a rumour last year that claimed that Apple would actually move its existing N3B chips to N3E, although many here said it isn't likely because the redesign costs would be prohibitive.

I don't know how accurate this would be, but knowing that the width of the chip is roughly 18-20% wider than the height, I plugged some numbers into this die per wafer calculator, using the default settings for the last 3 variables:

13.22 x 11.11 mm = 146.87 mm2 = 415 dies

View attachment 98270

I tried running the numbers again, this time with @repoman27's numbers, and this is the result:

12.64 x 10.67 mm = 134.87 mm2 = 458 dies.



However, as mentioned, Apple's own image showed 415 dies.

BTW, my 13.22 x 11.11 mm guesstimate from working backwards assumed that the width is 19% longer than the height. @repoman27's 12.64 x 10.67 mm puts the width at 18.5% longer than the height, so we're in the same ballpark there.

 

[repoman27]

The reason I believe my measurements are more accurate is because the source image that @Frederic_Orange started with is problematic. It's not really a photo of a wafer, it's a screen capture of an animation taken from the Apple keynote. That might be an undoctored yet dramatically lit video of an actual M3 wafer, or it might not. Let's say that it is. Just counting the gross die per wafer and plugging numbers into a die per wafer calculator until you get a match is not the best way to go about it—there are way too many variables involved.

However, we do know that the wafer itself is exactly 300 mm in diameter. So you can just count the maximum number of whole dies per row / column, add 1, and divide 300 by that number to arrive at a decent ballpark of the dimensions. In this case that works out to 13.6 mm x 11.5 mm = 156 mm², which isn't too far off. Measuring the dies themselves is more accurate.

I went frame by frame through the official version of Apple's "Scary Fast" event video in the highest resolution available and took a screen grab that I felt best showed the complete wafer. I opened that image in Photoshop and used the measurement tool with the measurement scale set to reflect the full diameter of the wafer being 300 mm. I then exactly measured the tallest column and widest row of complete dies, divided by the number of dies, and adjusted those numbers slightly for saw kerf. That yielded 13.3 mm x 11.1 mm = 148 mm². Despite my best efforts at avoiding error caused by foreshortening due to perspective, the ratio of those measurements does not exactly match the aspect ratio we find in Apple's M3 die shots. We also have no way of knowing if Apple stretched or altered the aspect ratio of any images provided in their marketing materials. The final issue is that measurements taken from a wafer include the full seal ring and scribe lanes, whereas Apple's die images appear to include some of the seal ring but are clearly cropped in slightly from what would be the die edge, so measurements taken from the die shots will be smaller than those based on wafer images.

The results from the two methods differ by a little less than 10%, so not a huge amount. However, if you want numbers that are comparable to the die sizes provided in the past by reverse engineering firms like TechInsights, I still believe the lower estimates I provided earlier are probably closer. I would love for TechInsights, Yole Group / SystemPlus, or Techanalye to throw us a bone and give us actual measurements for at least one of the M3 family chips.

 

[mikegg]

My more interesting question is: does Apple even have juice left in the tank on perf/GHz? Pace has been slow albeit they still lead by 10-15% over like the X4 or Nuvia.

No one knows besides the people on the chips but I'm guessing yes. I'm going to guess that the M4 generation will have a surprising improvement in IPC.

The CPU and GPU were both significantly redesigned but did not produce a high IPC improvement over A16. I'm guessing that Apple wanted to set the stage for optimizations after doing the hard work of redesigning the cores along with a brand new node.

 

[Mopetar]

If it is an M4 I would expect big gains. The only way it really makes sense for them to have M4 out only 7 months after M3 is if it were a new design being done by a different team that wasn't working on M3.

Another alternative is that we're getting an M3X or something that's basically an M3, but perhaps tailored to the iPad, and perhaps something else that Apple might want to put it in. Perhaps something designed for an even lower power target, etc.

 

[mikegg]

If it is an M4 I would expect big gains. The only way it really makes sense for them to have M4 out only 7 months after M3 is if it were a new design being done by a different team that wasn't working on M3.

I'm almost certain that Apple has some kind of leapfrogging teams system. There is no way that the same team designed all the M SoC.

 

[poke01]

I just thought of this, Apples P core is named Everest. Everest is the highest mountain in the mountain in the world or in other words it’s the highest peak. So Apples P core reached its peak.

This is an outlandish theory but what if Apple finally moves on from the Firestorm era IPC to a new completely new design in their next family of chips.

Or they started their P cores after mountains now.

 

[SpudLobby]

I'm almost certain that Apple has some kind of leapfrogging teams system. There is no way that the same team designed all the M SoC.

Well yeah for the whole SoC.

The CPU big core is what’s interesting. And not looking great long term, though it’s honestly impressive how it’s still ahead and they’re basically just riding our node stuff with frequency (which isn’t been fully iso-power with the A17/M3, it eats more and I think they pushed it too much) besides the extra cache and phydes changes.

In 3 years I wonder where Qualcomm and Arm will be by comparison

 

[Nothingness]

I just thought of this, Apples P core is named Everest. Everest is the highest mountain in the mountain in the world or in other words it’s the highest peak. So Apples P core reached its peak.

This is an outlandish theory but what if Apple finally moves on from the Firestorm era IPC to a new completely new design in their next family of chips.

Or they started their P cores after mountains now.

They can keep climbing by using solar system planets.

 

[soresu]

They can keep climbing by using solar system planets.

Or they can go in the negative direction with sea trenches.

 

[Doug S]

I'm almost certain that Apple has some kind of leapfrogging teams system. There is no way that the same team designed all the M SoC.

I think that's an outmoded way of looking at things. Back when chip architects were designing a "CPU", having two or three teams leapfrogging each other and when one finishes the 2024 design starting on 2026 or 2027 made sense. That's no longer true today when a chip design includes two different CPU core types, a GPU, an NPU, an ISP, and all the "uncore" like SLC/LPDDR5, USB and so forth.

I would guess they are organized along those lines, so perhaps you have one team doing CPU (or maybe even one doing P core and one doing E core) and another perhaps doing GPU/NPU/ISP, and another doing the uncore/everything else. There would be a team doing the overall A SoC and M SoC designs but they're working at a higher level integrating everything into a whole, and because they're working at a higher level they could work on multiple generations at once without leapfrogging required.

 

[Doug S]

Or they can go in the negative direction with sea trenches.

So if A18P cores are named Mariana we should expect a serious performance regression?

 

[Glo.]

So if A18P cores are named Mariana we should expect a serious performance regression?

Its so deep perf regression that you will count on your fingers faster than those chips.

 

[SpudLobby]

So if A18P cores are named Mariana we should expect a serious performance regression?

Lol. Yeah the Everest speculation is delusional. I honestly can’t believe the stuff we see here.

 

[SpudLobby]

I think that's an outmoded way of looking at things. Back when chip architects were designing a "CPU", having two or three teams leapfrogging each other and when one finishes the 2024 design starting on 2026 or 2027 made sense. That's no longer true today when a chip design includes two different CPU core types, a GPU, an NPU, an ISP, and all the "uncore" like SLC/LPDDR5, USB and so forth.

I would guess they are organized along those lines, so perhaps you have one team doing CPU (or maybe even one doing P core and one doing E core) and another perhaps doing GPU/NPU/ISP, and another doing the uncore/everything else. There would be a team doing the overall A SoC and M SoC designs but they're working at a higher level integrating everything into a whole, and because they're working at a higher level they could work on multiple generations at once without leapfrogging required.

Exactly.

 

[Mopetar]

If we do see an M4 that's got an actual new core as opposed to just reusing the same core while updating the model number (similar to how older generations of GPUs would just release the same cards with higher numbers) it would almost indicate that Apple has to have some leap frog teams arrangement.

For example around the time their first M-series chip was coming out, a separate team started working on a fresh design for what would eventually be the M4. Meanwhile the plan was for the M2 and M3 to be incremental improvements and tweaks to the existing design that would utilize the same cores that were going into the yearly iPhone models.

Otherwise it just doesn't make a lot of sense for an M4 that represents an actual new chip with new cores, etc. to show up this early. No one goes out of their way to plan on an 7/8-month cadence for their chip releases and even a 12-month cadence isn't going to be 4+ months ahead of schedule. A team that started work several years ago with a target of mid-to-late-2024, however, may have something to ready to go a bit sooner than an intended fall launch date.

 

[poke01]

Lol. Yeah the Everest speculation is delusional. I honestly can’t believe the stuff we see here.

I was spouting BS till the keynote. Just having some fun.

 

[Mopetar]

Mountains for core code names is pretty awesome though. I'm holding out for some Kilimanjaro cores.

 

[soresu]

So if A18P cores are named Mariana we should expect a serious performance regression?

Noooo it means DEEP core µArch 😂