Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[tamz_msc]

It already does

Kinda skeptical SKT can match GLC.

If it sounds too good to be true, then it probably is...

It already does though, at least in int. Normalize the SPECint 2017 data from the Anandtech review and see for yourself.

 

[uzzi38]

They can support different data types. But, they often do not. This link below is an Intel graphic, so it is obvious that it is geared to put Intel in the best light, but you can see that not all NPUs ran FP16 at the time of the image creation. If anyone can find AMD's list of supported NPU data types, then I'll link that as well (my Google skills are failing me, the latest information I found is that the list of supported data types has not yet been released).

https://cdn.wccftech.com/wp-content/uploads/2023/12/2023-12-14_19-47-23-1456x819.png

It literally took me about 20 seconds to find these:

AI Engine Technology

www.xilinx.com

 

[Henry swagger]

Kinda skeptical SKT can match GLC.

If it sounds too good to be true, then it probably is...

Apple did it with firestorm and is 8 wide 600+ robs

 

[AMDK11]

I will try to make a forecast regarding IPC Skymont. I believe that since Gracemont's IPC is approximately at the level of Skylake, Skymont will reach the level of SunnyCove or SunnyCove+. The GoldenCove level is a bit like saying that LionCove will offer an average IPC increase of +30-40%. I have nothing against higher IPC increases, but let's look realistically and coolly.

SunnyCove and GoldenCove ushered in a large core logic expansion and an average IPC increase of 18-19%.

LionCove will achieve an average IPC increase of 15-20%. Of course, the average of +10-15% may be less optimistic, but I have no such expectations or grounds to assume an increase of +25-30%.

LionCove Average IPC +15-20%
Skymont's average IPC at the level of SunnyCove or between SunnyCove and GoldenCove (optimistic forecast).

 

[SiliconFly]

Apple did it with firestorm and is 8 wide 600+ robs

Honestly, anything is possible. But a tiny E core hitting GLC levels is kinda hard to imagine.

It already does though, at least in int.

Sure. But overall performance like GLC? Thats a very massive jump. Makes it very difficult.

Skymont's average IPC at the level of SunnyCove or between SunnyCove and GoldenCove (optimistic forecast).

TBH, even hitting Sunny Cove performance is a tremendous win for Skymont. And even that isn't going to be that easy if you ask me. Should end up faster than Skylake for sure, but may finally land somewhere between Skylake & Sunny Cove. Feels more practical.

 

[AMDK11]

Yes. Even the SunnyCove level for 16 Skymont cores is a very big achievement and, rationally speaking, it is quite within reach. However, the level above SunnyCove is, in my opinion, the maximum in the forecast of average IPC growth.

 

[Anhiel]

To my knowledge Gracemont was 0.94 IPC compared to Sunny Cove. So only +6.3% would be needed. It's perfectly fitting for a single generational improvement. Considering & according to rumors, Lion Cove gets to be 8-wide instead of 6-wide. It seems the Skymont e-cores don't get that same expansion. Or that's a secret and there's more in store then.

Anyhow, last time I didn't take the new PowerVia into account:

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but Intel had been saying it would be coming along with Intel 20A and 18A and so forth.
So if we put faith into that we could see "30% platform voltage droop improvement and 6% frequency" as stated in their publication:

Request Rejected

Translated I assume that meant either another -30% power saving or +6% clockspeed.
Desktop Arrow Lake won't have on package memory so the raw performance result would be more or less remain the same compared to mobile but power saving would be more significant. So Intel could easily afford clockspeed regression while remaining competitve. On the Halo end sitll going for 5.8-6GHz will likely crush Zen5 in ST while still tie in MT.

 

[Anhiel]

So it seems some photo of Arrow Lake was leaked:

Intel Arrow Lake-H processor with 24 cores has reportedly been photographed - VideoCardz.com

Intel Arrow Lake processor for laptops has been pictured The 24-core variant of the upcoming Core Ultra 200 processor series has been shared by Moore’s Law is Dead. Intel is preparing to distribute qualification samples of its Arrow Lake processors to its partners. Although there’s an...

videocardz.com

From the looks of it the iGPU tile is about 2.85x14.39 mm^2 in TSMC N3 so that looks like 1.56x relative to Meteor Lake's 8 core iGPU with N5. Since it's said to only have 4 cores the rest would be just XMX? (taking up 2x space relatively) Or maybe it has additional NPU to those on the SOC.
Anyhow, the other SOC, IO tiles seem to remain with N6 or maybe N5.

 

[Hitman928]

Translated I assume that meant either another -30% power saving or +6% clockspeed.

Pretty sure the power savings doesn't work like that. I don't think we can say directly how much power savings you get from a Vdroop reduction.

 

[Anhiel]

Yeah, I guessed as much seeing how it was said.
Then the 6% clockspeed statement is a more reliable indication. On the higher end power would be more than 2x and approaching 1 on the lower end. Since they didn't say exactly where on the curve I assume it's the 3Ghz of the E-core given for 1.1V.

 

[SiliconFly]

Did a little more reading and came across this interesting old TP article. They've done a very good job testing out the E cores.

Intel Core i9-12900K E-Cores Only Performance Review

With Alder Lake, Intel is betting big on hybrid CPU core configurations. The Core i9-12900K has eight P(erformance) cores and eight E(fficient) cores. We were curious and tested the processor running the E-Cores only to see how well they perform against architectures like Zen 2, Zen 3, Skylake...

www.techpowerup.com

If you read it, you'll see that the gracemont E cores are already more closer to Sunny Cove than original Skylake, cos they're comparing them with 10th gen comet lake (a 4th gen Skylake architecture). So, if the newer Skymont E cores get a decent IPC uplift, they'll be more closer to Willow Cove or Golden Cove. Thats very exciting!

 

[AMDK11]

Intel itself placed IPC Gracemont at the Skylake level, but as we know, it may be weaker in one application and faster in another.

Of course we're talking about core vs. core.

IPC Skylake from 2015 to 2020 is practically no different. The core construction is identical. Of course, Cometlake uses, among others: with faster memories, larger L3 and a faster clocked ring bus.

WillowCove on average loses IPC to SunnyCove due to changing the cache subsystem from Inclusive(Skylake-SunnyCove) to Non-Inclusive(WillowCove).

 

[DavidC1]

To my knowledge Gracemont was 0.94 IPC compared to Sunny Cove. So only +6.3% would be needed. It's perfectly fitting for a single generational improvement. Considering & according to rumors, Lion Cove gets to be 8-wide instead of 6-wide. It seems the Skymont e-cores don't get that same expansion. Or that's a secret and there's more in store then.

Skymont is even bigger gain with 3x3 cluster decode with more than 20 ports(compared to 17 in Gracemont).

Don't forget that Crestmont is already 4-6% faster, and "Raptormont" is 1-3%, meaning Crestmont alone will make up for the gap.

All they have done on Crestmont at the high level is widening the retire/rename from 5-wide to 6-wide. One would logically assume a front end expansion of 50% would be greater than mere 6%.

It seems the Skymont e-cores don't get that same expansion. Or that's a secret and there's more in store then.

Also keep in mind the front-end stayed the same and called it Goldmont "Plus" resulting in many to conclude it would be a disappointment, when it turned out to be yet another 30% gain per clock, with higher clocks all at the same process and power.

LionCove will achieve an average IPC increase of 15-20%. Of course, the average of +10-15% may be less optimistic, but I have no such expectations or grounds to assume an increase of +25-30%.

That just means the E core and P core gains will be smaller than ever, resulting in a much better hybrid implementation with lot less scenarios for "jitter" as some might call it.

It isn't that the E core is exceptional, it's just in comparison the P core efficiency(die area/power efficiency) is so bad and is in dire need of drastic improvement in execution. Think of how the Core humiliated the main core line, Netburst.

Apple did it with firestorm and is 8 wide 600+ robs

Likewise(although not as low), the E cores have lot less pipeline stages and that alone gets it 2-4% every pipeline stage.

10-stage pipeline for Apple Ax means that with 60% hit rate of the uop cache, the 15-19 stage of Golden Cove is effectively a 17 stage part, so branch mispredict penalty alone gives Ax core anywhere from 14-28% advantage per clock. So a typical "full" Intel generation advantage is merely due to pipeline stage differences. In other words, Sunny Cove at 10 stage pipeline would have performed like Golden Cove or better, with a simpler, more power efficient design.

In reality, a full 10 stage optimized hypothetical "Sunny Cove" would have performed noticeably better than GLC because by aiming at lower clocks, things like cache latency would be improved, and critical levels like L1 could be significantly enlarged.

 

[DavidC1]

Intel itself placed IPC Gracemont at the Skylake level, but as we know, it may be weaker in one application and faster in another.

The hard part of architecture is general purpose Integer. FP is where the P cores are really ahead but it benefits disproportionately with things such as adding more FP units, or widening the L/S unit. The branch mispredict penalty likewise does not take into account FP pipeline stages, despite the fact that it's significantly longer, as FP workloads are easier to parallelize and consequently less "branchy".

Integer on the other hand requires smarts that do not come from merely throwing money and requires real thought and creativity from the engineers to constantly improve performance while at the same time needing to balance power, transistor budget, and TTM.

The good thing about aiming general purpose Integer is that it benefits ALL workloads(Integer, FP, AI, etc), and any work on top of that is merely icing on the cake.

 

[AMDK11]

I don't expect such a drastic change as moving from Netbrust with low IPC (lower than PIII and Banias (design choice)) to Conroe. GoldenCove already has a very high IPC reaching very high clock speeds.

Yes, LionCove may be a change of approach with a shorter pipeline with fewer steps. LionCove could hypothetically have "smarter" designed logic to make better use of resources, but I don't think the IPC increase would be dramatic. If it's different, I'll be excited.

 

[tamz_msc]

AFAIK, Intel claims that Gracemont has the same performance, not IPC, as Skylake.

Like I said before - Gracemont and Golden Cove IPC is almost identical in integer workloads.

 

[DavidC1]

Yes, LionCove may be a change of approach with a shorter pipeline with fewer steps. LionCove could hypothetically have "smarter" designed logic to make better use of resources, but I don't think the IPC increase would be dramatic. If it's different, I'll be excited.

The fact that the mill suggests 33% wide front end and nearly 50% more ROB and maybe 20% gain suggests it's nothing special and is a mere expansion just like every P generation since Sandy Bridge. If anything, overall it's worse as the clocks are supposed to go down.

This may be the worst generation until they change direction with Nova Lake in late 2026.

Like I said before - Gracemont and Golden Cove IPC is almost identical in integer workloads.

Golden Cove is 40% faster in SpecCPU with the split being 25% Integer and something like 40-50% FP. The SpecCPU differences are roughly reflected in Geekbench as well.

 

[eek2121]

Honestly kind of baffled why you guys think it won’t be touching golden cove in terms of performance (unless you only meant IPC/PPC).

Process improvement alone would get them most or all of the way there (just from increased clocks)

Now don’t misunderstand, just like Gracemont lagged behind skylake in many areas, so likely will skymont.

 

[FlameTail]

This may be the worst generation until they change direction with Nova Lake in late 2026.

I thought Arrow Lake was supposed to be the generation where things changed in a new direction?

First tiled architecture for desktops, First RibbonFET and PowerVia product, Lion Cove core designed with Jim Keller's involvement, etc...

 

[AMDK11]

Conroe (Core 2) was a big change in the approach to PC core design compared to Netbrust (Pentium 4). Despite the drastic changes and leadership in x86, Conroe is Core 2 compared to mobile Yonah (Core(1)), which is actually a major development of x86.

I wouldn't attach much importance to generation names and interpretations in relation to revolutions etc.

NovaLake may not be about the IPC increase itself, but, for example, the implementation of x86s, a leading technological process or the lowest or comparable energy demand.

LionCove could mean a big change in approach.

Fortunately, ArrowLake is closer rather than farther.

 

[SiliconFly]

I thought Arrow Lake was supposed to be the generation where things changed in a new direction?

Arrow Lake is supposed to be the generation where things are expected change in a new/better direction.

 

[eek2121]

Arrow Lake is supposed to be the generation where things are expected change in a new/better direction.

One could argue meteor lake is that chip. People keep saying it is underwhelming, but it was a huge step in the right direction for Intel. They get their chiplet stuff worked out and it is more power efficient than raptor lake.

Arrow Lake will take this up a notch in terms of both performance and efficiency.

I'm actually really interested in Lunar Lake. I hope it lands in some interesting places (like an SBC).

 

[SiliconFly]

One could argue meteor lake is that chip. People keep saying it is underwhelming, but it was a huge step in the right direction for Intel. They get their chiplet stuff worked out and it is more power efficient than raptor lake.

True. MTL was supposed to be their first step in the right direction. Everything including the GPU, NPU & SoC tile, LPE cores, EUV node, Foveros packaging, etc were excellent. But MTL has the outdated + inefficient + noncompetitive RWC P cores which by no means is a good thing imho. They wanted to de-risk, took the safest route and ended up with a subpar product. Has good efficiency uplift, but not much performance. I mean the performance uplift is pretty much non-existent, and in rare cases, there's even regression.

Arrow Lake will take this up a notch in terms of both performance and efficiency.

ARL will be their first true product in the right direction (with absolutely no legacy stuff). I think it's definitely going to be very efficient. But LNC's performance is still a question. It may end up with just mediocre uplift or might be extremely high like a few suggested. Very hard to guess. But it's very clear that Arrow Lake's future now squarely depends on LNC's performance. LNC is make or break for Intel. If LNC tanks, we can all (and should) say goodbye to Intel and move on.

I'm actually really interested in Lunar Lake. I hope it lands in some interesting places (like an SBC).

Lunar Lake is definitely very interesting. But one thing that bothers me is, people in general are giving it too much importance (considering the fact it's just a low volume niche product). More like a tech demo. Creating a new market takes many years. Even it's successor panther lake I think might have trouble hitting decent volume.

 

[FlameTail]

Lunar Lake is definitely very interesting. But one thing that bothers me is, people in general are giving it too much importance (considering the fact it's just a low volume niche product). More like a tech demo. Creating a new market takes many years. Even it's successor panther lake I think might have trouble hitting decent volvolume.

Isn't Panther Lake supposed to be the next MTL-like generation? Mobile focused but high volume (MTL, TGL).

 

[Geddagod]

ARL will be their first true product in the right direction (with absolutely no legacy stuff).

iGPU is recycled from MTL, as is SOC tile and the rest of the setup.

It may end up with just mediocre uplift or might be extremely high like a few suggested.

Idk how many times I say this, and you just ignore it, but again, it's literally only MLID who expects a high performance uplift. Literally everyone else, Xino, Raichu, etc etc all say the perf uplift is gonna be ~10% over RPL.

LNC is make or break for Intel. If LNC tanks, we can all (and should) say goodbye to Intel and move on.

That's such an over reaction lol.

But one thing that bothers me is, people in general are giving it too much importance (considering the fact it's just a low volume niche product).

Who said it was low volume?

More like a tech demo. Creating a new market takes many years.

That market has been there for a while, Intel has just been a very bad participant in it. Apple is much better at that.