Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[mikk]

Because Lunar Lake comes too early, this is not an option. The generation after Lunar lake it is. Most people got the roadmap wrong and think LNL is on 18A+external.

 

[igor_kavinski]

Why not both?

TSMC chips don't clock higher than Intel fabbed chips. I suppose Intel could use the TSMC chips in Core 3 and 5 series. But part of me thinks Intel won't use TSMC unless they absolutely have to coz their own fab engineers messed up again and then it's gonna be TSMC only.

 

[cebri1]

Can’t answer most of the question but Lunar Lake is N3B not 18A

For the GPU tile I understand.

 

[Ajay]

Because Lunar Lake comes too early, this is not an option. The generation after Lunar lake it is. Most people got the roadmap wrong and think LNL is on 18A+external.

Panther Lake?

 

[mikk]

Panther Lake?

Panther Lake is using 18A confirmed by Intel. It could still use external like ARL 20A+N3, although I wouldn't expect it. I believe with 18A there is no need for external help for the compute tile.

 

[Hulk]

New process tech is developed in Oregon.

It begins with research stage where the characteristics of the node are developed (number of layers, chemistry, etc.). This transitions to Initial Development where they try to get the process to yield. After initial development they attempt volume production and if that works it’s ready to be exported to another Intel fab to enter HVM (I think this is what they mean by manufacturing ready).

So a product like ARL on a new process could most likely have ES chips fabbed at Oregon.

Thanks for responding. This makes perfect sense. I assume they have the exact same equipment as the productions facilities so when they figure out how to get the process working/yielding they can send their data to the appropriate production facility.

Does this mean that the Oregon facility has all of the equipment to produce parts from ingots to packaged chips or are the wafer produced in Oregon and then cut, packaged somewhere else?

I realize that much of this information is proprietary. I'm curious as to how much IS known.

 

[mikk]

Hardware design for MTL notebooks has been finished, software and driver optimization work remains for the next two months.

Laptops equipped with the next-generation Core processor, Core Ultra (Meteor Lake), which Intel officially unveiled at the 'Intel Innovation' event in mid-September, are expected to be released in large numbers in markets around the world, including Korea, as early as the end of this year.

However, according to officials from several PC manufacturers, these companies have already completed the design of hardware such as the motherboard and external design based on the Core Ultra processor prototype supplied by Intel. Only software and driver optimization remains for the next two months.

Rather, the biggest factor affecting release time appears to be software and driver optimization. Another manufacturer official explained, “Over the next two months, the key will be software optimization using the NPU built into the SOC tile along with drivers related to the Arc graphics chipset, which will be built for the first time in the Core Ultra.”

https://zdnet.co.kr/view/?no=20230929213515

 

[AMDK11]

The data regarding the number of transistors per core that I provided for SunnyCove are from a lecture by Jim Keller posted on YouTube from the article below:

Intel’s next-gen CPU architecture will be “significantly bigger” than Sunny Cove

Jim Keller is touting a performance boost that scales "closer to the linear curve" relative to increases in transistor count

www.pcgamesn.com

x86 Skylake ~217 mln Tr
x86 Cypress/SunnyCove 300 mln Tr(+38%)

Edit:
It's hard to say whether Jim, when he talks about a window of 800 microinstructions and 3 to 6 instructions, means the next-generation core after GoldenCove?If so, it's possible that this new generation will be LionCove, which most likely still has a 6-way x86 decoder but including 6 ALU.

 

[mikk]

Another Lunar Lake entry....


Intel LNL-M LP5 RVP1
Genuine Intel(R) 0000 1.00GHz (5M 20c 3.91GHz + 2.61GHz, 3.3GHz IMC, 4x 2.5MB + 4MB L2, 2x 8MB L3)
Number of Devices / Threads 1 / 8

Details for Result ID Genuine Intel(R) 0000 1.00GHz (5M 20c 3.91GHz + 2.61GHz, 3.3GHz IMC, 4x 2.5MB + 4MB L2, 2x 8MB L3)

ranker.sisoftware.co.uk

3.91 Ghz for Lion Cove and 2.61 Ghz for Skymont? 5M 20c is confusing to me, the threads number however matches the 4+4 +SMT disabled rumor. Sisoft reports 17W of power, no idea if accurate. GPU benchmark says 8W. Maybe 17W PL2 and 8W PL1, just a guess.

 

[trivik12]

Impressive that we are seeing benchmarks for a product not launching for another year. I wonder when Intel will confirm node for LNL.

 

[igor_kavinski]

Impressive that we are seeing benchmarks for a product not launching for another year.

They are deliberately doing that. Want the world to know that they are ON TRACK.

 

[Hulk]

While we wait for Raptor Refresh and Meteor Lake here is a little chart to tide us over. I added the Zen cores to it.

 

[igor_kavinski]

View attachment 86694

Henry's gonna love this chart, that's for sure.

 

[Markfw]

Henry's gonna love this chart, that's for sure.

But it say nothing about points/watt.

 

[igor_kavinski]

But it say nothing about points/watt.

There's a recent news piece about Microsoft looking into the possibility of a nuclear reactor for its data centers. Must've gotten a really sweet deal on thousands of SPR chips

Found it: https://www.extremetech.com/energy/...se-nuclear-reactors-to-power-its-data-centers

 

[Geddagod]

3.91 Ghz for Lion Cove and 2.61 Ghz for Skymont?

Imagine it's the other way around, lol

5M 20c is confusing to me

Same

4x 2.5MB + 4MB L2,

2.5MB L2 up from 2MB for P cores, while the E cores' L2 stays the same? Wonder how the new P-core extra layer of cache is being reported, is it being combined with the L2 for the 2.5MB figure, or what? I'm guessing it's not.

2x 8MB L3

This seems awfully low...

I wonder when Intel will confirm node for LNL.

They are just delaying the inevitable stock price plummet when they officially announce they will be using TSMC lol

They are deliberately doing that. Want the world to know that they are ON TRACK.

They just did that when they demo'd LNL at their recent event

While we wait for Raptor Refresh and Meteor Lake here is a little chart to tide us over. I added the Zen cores to it.

View attachment 86694

I was going to wonder at what frequency you used for each of these cores to calculate it, but I'm also pretty sure CBR23 scales really well with clocks in terms of maintaining the same PPC at a wide range of clocks... at least for the more recent architectures. Also, no SNC and WLC? :c Cool chart tho

But it say nothing about points/watt.

Says nothing about total ST score either or max ST freq either.
Points/watt is a terribly hard metric to calculate since the points/watt depends on how hard you're clocking it, so it would require a lot of data/testing.

There's a recent news piece about Microsoft looking into the possibility of a nuclear reactor for its data centers. Must've gotten a really sweet deal on thousands of SPR chips

Intel chips power hungry haha I did a funny
lol

 

[igor_kavinski]

They just did that when they demo'd LNL at their recent event

Following that up with public benchmarks to let the world know that they weren't lying at the event. They are desperate to make the world believe that they will hit their targeted milestones, even if it's CPUs with +5% IPC.

 

[Geddagod]

Following that up with public benchmarks to let the world know that they weren't lying at the event.

You're reaching too hard man. I really don't think it's that deep, nor do I think any serious major investors would care about this. It's fun for the casuals who like discussing leaks ig...

They are desperate to make the world believe that they will hit their targeted milestones,

Well ye

even if it's CPUs with +5% IPC.

Don't know what that's even supposed to mean tbh

 

[igor_kavinski]

Don't know what that's even supposed to mean tbh

It means if they had a new arch but it was held back by frequency regression due to immature node, they would still release it coz in their state of affairs, ANY progress is good progress.

 

[Geddagod]

It means if they had a new arch but it was held back by frequency regression due to immature node, they would still release it coz in their state of affairs, ANY progress is good progress.

I mean, it looks like Intel has been doing a similar shtick for a while, though it hasn't been a regression as much as stagnation. 14,22, and 32 all seemed to have stagnated/regressed.
And ye, any progress is good progress, but I feel like your downplaying the significance of perf/watt, not just perf. The node shrinks help perf/watt a good bit, even if perf doesn't move the needle much.
And that's generally fine, because Intel releases in a yearly schedule vs AMD's more 1.5 year cycle.
Intel's behavior isn't due to their "current state of affairs". They have done exactly this in the past.

As for specifically in the future, MTL has a freq regression sure, but I also think the fact that Intel has like 3 extra iterations on their 10nm node kinda skews the "regression" claim. That's not so much on the new node as much as the old node just being extremely mature. That and the other architectural changes RWC has, which makes clocking higher harder.
As for ARL, the fact that both TSMC N3 and Intel 20A are rumored to have bad perf makes it sound like LNC problems are a fundamental architectural one (even if it's clocks, maybe the arch itself is very hard to clock super high).

 

[Hulk]

But it say nothing about points/watt.

 

[rtxtwt]

LunarLake-M
edit: already posted, ouch

They are deliberately doing that. Want the world to know that they are ON TRACK.

Maybe not necessary to do that, what I heard is some NDA guys already touched LNL samples last month. Maybe this guy was careless and upload the results.

 

[H433x0n]

They are just delaying the inevitable stock price plummet when they officially announce they will be using TSMC lol

I don't think we'll get concrete info on which node is used for the different ARL SKUs up until literal launch day. Same goes for LNL.

 

[H433x0n]

Following that up with public benchmarks to let the world know that they weren't lying at the event. They are desperate to make the world believe that they will hit their targeted milestones, even if it's CPUs with +5% IPC.

Pretty sure it'll be more than +5% IPC, it's the big frequency regression that holds back it's ST performance. Even if they manage to get boost clocks to 5.2ghz (who knows if they even manage that tbh) it's got to overcome RPL-R's 15% higher frequency with raw IPC just to break even.

As for ARL, the fact that both TSMC N3 and Intel 20A are rumored to have bad perf makes it sound like LNC problems are a fundamental architectural one (even if it's clocks, maybe the arch itself is very hard to clock super high).

I would say how well it clocks on 20A at the moment isn't much of an indication since we're still pretty far out from that node going into HVM.

 

[igor_kavinski]

Even if they manage to get boost clocks to 5.2ghz (who knows if they even manage that tbh) it's got to overcome RPL-R's 15% higher frequency with raw IPC just to break even.

That's my problem with Intel's approach. Instead of refining Intel 4 (and they already failed on it with MTL-S), they will tackle a new node and new architecture at the same with ARL-S on Intel 20A. Sounds like a recipe for delay/disaster. At least this time, maybe they will still get to release the CPU on time by using N3 so it might be the first ever iso-process battle between Intel and AMD, at least for the compute tiles. The best comparison would be if AMD were to use IFS for their entire CPU package and with Intel not holding back any fab advantage for themselves.