Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[rtxtwt]

These documents which are leaked by yuuki_ans seems imply the Hyperthreading(SMT) is still there in the ARL P core, but it cause some mobo function like M2 SSD misfunction the SMT was turned of on initial ES ARL SKUs.
Some terminology/key words are expunged(by yuuki_ans?) and leave blank, but it is easy to guess though.

 

[Dayman1225]

These documents which are leaked by yuuki_ans seems imply the Hyperthreading(SMT) is still there in the ARL P core, but it cause some mobo function like M2 SSD misfunction the SMT was turned of on initial ES ARL SKUs.
Some terminology/key words are expunged(by yuuki_ans?) and leave blank, but it is easy to guess though.

View attachment 92133

I’m understanding it a bit differently, I’m reading it as the 8c 8t P Cores(“IA cores”) are disabled in bios due to instability bug with only e cores enabled

 

[SiliconFly]

That website is cancer. Remember when they said Zen would have 512MB of L3 cache? Years before 3D cache was a thing.

That website is trash. But the yuuki_ans leak looks legit.

These documents which are leaked by yuuki_ans seems imply the Hyperthreading(SMT) is still there in the ARL P core.

It clearly states 8 P cores / 8 Threads. So no HT. (IA -> P cores)

 

[Dayman1225]

I’d also like to point out this is “pre alpha” probably for power on and early validation. So it is not ES1 or ES2. Assuming it says 3.5Ghz, that is quite good for Skymont E cores on such an early chip

 

[DrMrLordX]

Source?
Cause someone just mentioned Intel has 288cores planned...

IIRC they showed a 2S system with 2 x 144C, but well, we should have some news sooner or later.

Last I saw, the 288c Sierra Forest system was 2P or like Cascade Lake-AP (2P in one socket).

In other words, the high core-count dice had been cancelled.

edit @QuickyDuck beat me to it

 

[Abwx]

Last I saw, the 288c Sierra Forest system was 2P or like Cascade Lake-AP (2P in one socket).

In other words, the high core-count dice had been cancelled.

edit @QuickyDuck beat me to it

If 144C require 360W it doesnt make sense to cram 288C for this TDP, that s silicon waste as long as it s with the same process.

 

[DrMrLordX]

If 144C require 360W it doesnt make sense to cram 288C for this TDP, that s silicon waste as long as it s with the same process.

Tell that to Intel. It wasn't my idea.

 

[SiliconFly]

If 144C require 360W it doesnt make sense to cram 288C for this TDP, that s silicon waste as long as it s with the same process.

Bergamo is around 400W. So, SF 288C can comfortably go up to 450W which should be quite sufficient.

 

[eek2121]

That website is cancer. Remember when they said Zen would have 512MB of L3 cache? Years before 3D cache was a thing.

The site IS garbage, but all future Intel chips will have higher base clocks thanks to process improvements. Even Meteor Lake has higher base clocks.

 

[Anhiel]

It does look like only HT has been turned off rather than a specific ST only design. Welp, I guessed as much last year.
It's been shown before Skylake/ADL without HT gains ~24% (outliers 31%) for ST. Since the MT gains aren't as large as Zen's ofc it means Intel's has a bigger loss in MT mode for the 1st thread and 2nd thread. Since Zen is able to keep higher rates for the 1st and 2nd threads and only gets ~12% w/o SMT. Zen would have more too lose so this cheap trick won't work for Zen. Sooner or later HT will have to return imho.

 

[S'renne]

It does look like only HT has been turned off rather than a specific ST only design. Welp, I guessed as much last year.
It's been shown before Skylake/ADL without HT gains ~24% (outliers 31%) for ST. Since the MT gains aren't as large as Zen's ofc it means Intel's has a bigger loss in MT mode for the 1st thread and 2nd thread. Since Zen is able to keep higher rates for the 1st and 2nd threads and only gets ~12% w/o SMT. Zen would have more too lose so this cheap trick won't work for Zen. Sooner or later HT will have to return imho.

That's what the E cores are for, and ARM CPUs doesn't use SMT but is still competitive in MT

 

[SiliconFly]

It does look like only HT has been turned off rather than a specific ST only design. Welp, I guessed as much last year.
It's been shown before Skylake/ADL without HT gains ~24% (outliers 31%) for ST. Since the MT gains aren't as large as Zen's ofc it means Intel's has a bigger loss in MT mode for the 1st thread and 2nd thread. Since Zen is able to keep higher rates for the 1st and 2nd threads and only gets ~12% w/o SMT. Zen would have more too lose so this cheap trick won't work for Zen. Sooner or later HT will have to return imho.

LNC is a grounds up new design. So, HT hasn't been turned off. It was never implemented. Starting with LNC, they're trying to follow the likes of Apple Silicon which offers higher performance without HT or SMT. So, HT isn't coming back.

And considering the numerous cores CPUs have these days, HT doesn't make sense anymore. HT is purely for MT gains, and it offers performance benefit only when all the existing cores are already maxed out. HT based thread context switching is significantly faster when compared to a OS based context switch. That is it's sole purpose. Throwing more E cores into the mix and improving the performance of E cores should take care of MT perf without HT. Keeps P core design neat & clean.

Also, I remember reading that the new LNC P cores are going to be larger than RWC P cores! Don't know how far it's true, but looks like that might be the case. LNC's primary focus seems to be ST performance more than MT performance.

 

[trivik12]

SquashBionic is saying ARL-U is Intel 3. Not sure if he is reliable. But I see multiple articles quote him as source.

https://twitter.com/x/status/1747981927020449985

 

[SiliconFly]

SquashBionic is saying ARL-U is Intel 3. Not sure if he is reliable. But I see multiple articles quote him as source.

If it's MTL-U refresh on intel 3, then it's not worth anybody's time.

 

[SpudLobby]

If it's MTL-U refresh on intel 3, then it's not worth anybody's time.

Eh.
What actually sucks is that it’s MTL, not Intel 3. That part is interesting. Should see see real performance/watt and density gains. Not enough to take away from the primary issue with MTL — or ARL’s crap — but still. Academically interesting.

 

[trivik12]

Since Intel 3 is refined Intel 4, clock speeds should be higher. That said I am not sure about Intel's strategy here. Anyway we will know details probably around September when Intel On event is hosted.

 

[moinmoin]

Keeps P core design neat & clean.

Also, I remember reading that the new LNC P cores are going to be larger than RWC P cores!

I personally wouldn't think of calling those monster P cores whose size was the reason to introduce E cores to begin with "neat & clean". Also I find it really odd that HT gets removed but the design apparently is not redone enough to make the area usage any more efficient.

 

[gdansk]

Arrow Lake is meh

How do you know this?

 

[coercitiv]

Also I find it really odd that HT gets removed but the design apparently is not redone enough to make the area usage any more efficient.

I would not be surprised if SMT circuitry is still there. Remember when they told us they had removed AVX512 transistors from Lakefield?

Knowing that Lakefield was going to have to take the lowest common denominator from the two core designs, Intel probably should physically removed the very bulky AVX-512 unit from the Sunny Cove core. Looking at the die shot, it's still there - there was some question going into the recent disclosures as to whether it would still be there, but Intel has stated on the record repeatedly that they removed it. The die shot of the compute silicon shows that not to be the case.

 

[poke01]

How do you know this?

I am guessing from the way Intel is projecting it.

 

[uzzi38]

SquashBionic is saying ARL-U is Intel 3. Not sure if he is reliable. But I see multiple articles quote him as source.

https://twitter.com/x/status/1747981927020449985

Bionic literally has slides on hand (that I've seen, so I know they exist). He's as reliable as you can ask for.

 

[SiliconFly]

...I find it really odd that HT gets removed but the design apparently is not redone enough...

Wrong. LNC is a grounds up new design started under Keller's supervision. So, HT hasn't been "removed". It was never implemented. Starting with LNC, they're trying to follow the likes of Apple Silicon which offers higher performance without HT or SMT.

 

[moinmoin]

Wrong. LNC is a grounds up new design started under Keller's supervision. So, HT hasn't been "removed". It was never implemented. Starting with LNC, they're trying to follow the likes of Apple Silicon which offers higher performance without HT or SMT.

Don't you think it's highly worrying that LNC is supposed to be a ground up new design but supposedly already larger than RWC?

 

[S'renne]

Don't you think it's highly worrying that LNC is supposted to be a ground up new design but supposedly already larger than RWC?

Isn't this what Intel wants though, large P cores with E cores around it

 

[moinmoin]

Isn't this what Intel wants though, large P cores with E cores around it

Even if Intel wants to keep that setup in the long run, they would want to make the P cores area competitive to all the competition out there.