Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Doug S]

That’s for Intel 4, not 18A.

The important thing is that it showed that BSPDN allows relaxing M0 metal pitch without affecting density. The same will apply to 18A. M0 will be larger for 18A than it would have been without PowerVIA.

We'll see the same thing with TSMC's initial N2, and the version of N2 coming six months later (i.e. the one that Apple will use) that offers BSPDN as an option. It isn't clear if BSPDN will be mandatory in N2P but from the sound of things it will remain optional as they claim to have some customers that don't want it to save money (whether it actually costs TSMC more or they are just charging more for it intially isn't known I guess)

 

[Ghostsonplanets]

Too bad Ghostsonplanets is wrong with his tile prediction. Just because LNL integrate Soc into the compute tile doesn't mean Intel will do the same with their regular mobile lineup after Arrow Lake. Why should they do this if they are 18A volume limited. Panther Lake is not a MX chip, it's UPH. There is no On-package memory either based on the Intel slide.

Prediction? I believe this was the rumored upon Tile configuration of PTL until Tigerick said that there's actually 3 tiles (+base). Intel wanted to reduce the heavy handed tile approach of MTL/ARL, hence why the reduction in tiles.

Even then, the claimed CPU tile is still absorbing the SoC tile, NPU, MEDIA Engine, etc into a single tile. With PCD replacing IO and the tGPU being separate like MTL.

I also never claimed it was a LNL MX follow-up sucessor. I even questioned why l, so far, PTL has no indicative of following up LNL or having a LNL like SKU.

 

[mikk]

Prediction? I believe this was the rumored upon Tile configuration of PTL until Tigerick said that there's actually 3 tiles (+base). Intel wanted to reduce the heavy handed tile approach of MTL/ARL, hence why the reduction in tiles.

Even then, the claimed CPU tile is still absorbing the SoC tile, NPU, MEDIA Engine, etc into a single tile. With PCD replacing IO and the tGPU being separate like MTL.

I also never claimed it was a LNL MX follow-up sucessor. I even questioned why l, so far, PTL has no indicative of following up LNL or having a LNL like SKU.

The only credible rumor was a 3 tile design xino mentioned. Tigerick was wrong in the beginning, however the newer/corrected info he posted sounds legit because it's more detailed.

To me it's a summary of leaks combined from other people what Prakhmar posted, most of the stuff he told wasn't new to me. It's not like he faked it. It doesn't mean everything is correct though. I was sceptical about the 4+8+4 core config but now I think it makes sense, they can reuse the Lunar Lake layout with the 4 LPE cluster and add 8 E cores into the ringbus. They can shut down the ringbus cores and L3 in lower load scenarios as with Lunar Lake. LPE cores should be much more useful on the same node and tile and twice the cores count, on MTL it was underwhelming.

 

[Henry swagger]

Gracemont in Alder Lake already is ~95% of the per-clock integer performance of Cypress Cove. In Raptor Lake, it should surpass the PPC of Cypress Cove. Skymont should at minimum be Golden Cove level of PPC.

All this is based on the SPECint_rate 2017 1T numbers from past Anandtech reviews.

Even leaks said its targeting golden cove ipc.. skymont will be 8 wide

 

[Hulk]

I have come to the conclusion that MTL will always be somewhat of a mystery performance-wise. It's hard to lock these mobile parts down to a frequency to isolate them for "throughput" and efficiency tests I guess. In my head right now when I think of MTL I think, performance at least as good as RPL mobile but with better efficiency and much better iGPU. But I have no objective metrics that readily come to mind that I have faith in.

I think Intel may have an opportunity with Lunar Lake. As we know memory subsystem performance has always been the achilles heel for mobile systems. Putting main memory on the tile hopefully will alleviate some of discrepancy between desktop and mobile performance.

 

[Ghostsonplanets]

I have come to the conclusion that MTL will always be somewhat of a mystery performance-wise. It's hard to lock these mobile parts down to a frequency to isolate them for "throughput" and efficiency tests I guess. In my head right now when I think of MTL I think, performance at least as good as RPL mobile but with better efficiency and much better iGPU. But I have no objective metrics that readily come to mind that I have faith in.

I think it's best to think of MTL as a TGL, even if a bit disjointed due to the first step into a disaggregated architecture.

It's a genuinely good product, even if it can't best the competition. CPU performance is a bit lackluster, but it has an amazing GPU IP, best in class Media and Display Engine, good ISV support for NPU and AI workloads. It's also an amazing leap in perf/W, efficiency and battery life for Intel, specially coming from "No battery" Alder/Raptor "No life" Lake Mobile.

If you can buy a laptop with MTL, specially 6+8 and with decent pricing, it's a no brainer. Or you can wait for ARL-U to bring a 10% bump in efficiency for the Compute Tile alongside a price reduction and higher availability.

I think Intel may have an opportunity with Lunar Lake. As we know memory subsystem performance has always been the achilles heel for mobile systems. Putting main memory on the tile hopefully will alleviate some of discrepancy between desktop and mobile performance.

I think Lunar Lake will be one of the most significant launches for Intel. As you say, they have a very interesting opportunity to turn around the x86 performance and battery life discourse while also offering a flexible chip that can go into either fanless or fanned and enabling novel PC designs. Genuinely (IMO), the most interesting launch from Intel this year.

 

[Gzxy]

I just answered that here: http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...akes-discussion-threads.2606448/post-41190543

Intel doesn't have capacity. Intel doesn't have capacity. Intel doesn't have capacity. What part of that are you struggling with? If you need me to say it another way: Intel bought too little equipment and is maxed out on their top nodes.

So rather than build only your own chips in your fabs, you build other people chips in your fabs and you outsource yours in TSMC since you cant risk having huge capacity if IFS fails and maybe your future nodes aren't very competitive. Also use some of your own capacity for server chips (Xeon) where margins are better.

 

[Hulk]

I think it's best to think of MTL as a TGL, even if a bit disjointed due to the first step into a disaggregated architecture.

It's a genuinely good product, even if it can't best the competition. CPU performance is a bit lackluster, but it has an amazing GPU IP, best in class Media and Display Engine, good ISV support for NPU and AI workloads. It's also an amazing leap in perf/W, efficiency and battery life for Intel, specially coming from "No battery" Alder/Raptor "No life" Lake Mobile.

If you can buy a laptop with MTL, specially 6+8 and with decent pricing, it's a no brainer. Or you can wait for ARL-U to bring a 10% bump in efficiency for the Compute Tile alongside a price reduction and higher availability.


I think Lunar Lake will be one of the most significant launches for Intel. As you say, they have a very interesting opportunity to turn around the x86 performance and battery life discourse while also offering a flexible chip that can go into either fanless or fanned and enabling novel PC designs. Genuinely (IMO), the most interesting launch from Intel this year.

I'm seriously considering that Zenbook 14 that Anandtech used to review MTL. I checked one out at MC and it was very impressive. I'm using a 6 year old Surface Laptop 2 that quite honestly has been a fantastic device. But times have caught up with it. The iGPU is useless for video editing. Topaz video/photo AI, and PureRaw, which I use quite often. Also the 4 Skylake cores are overmatched for many of my apps.

I've been waiting and waiting for the Surface Laptop 6 and am super eager to upgrade so I don't have to go to my desktop every time I need to do something compute intensive.

 

[igor_kavinski]

View attachment 86104

View attachment 86105

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

View attachment 90388

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

View attachment 90627

Can you update your post to include this link? http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...akes-discussion-threads.2606448/post-41187952

Would be helpful for new readers.

 

[igor_kavinski]

I'm seriously considering that Zenbook 14 that Anandtech used to review MTL. I checked one out at MC and it was very impressive.

Would that be the best performance for your dollar, considering the impending launch of a tiny little chip from a tiny little company called AMD?

 

[tamz_msc]

I'm seriously considering that Zenbook 14 that Anandtech used to review MTL. I checked one out at MC and it was very impressive. I'm using a 6 year old Surface Laptop 2 that quite honestly has been a fantastic device. But times have caught up with it. The iGPU is useless for video editing. Topaz video/photo AI, and PureRaw, which I use quite often. Also the 4 Skylake cores are overmatched for many of my apps.

I've been waiting and waiting for the Surface Laptop 6 and am super eager to upgrade so I don't have to go to my desktop every time I need to do something compute intensive.

Nah, get the IdeaPad 5 Pro - it comes with LPDDR5x-7467.

 

[igor_kavinski]

IdeaPad 5 Pro

Other than the Thinkpad, their keyboards are usually awful.


They are probably the only ones who insist on making keys shaped that way.

 

[tamz_msc]

Other than the Thinkpad, their keyboards are usually awful.

View attachment 96994
They are probably the only ones who insist on making keys shaped that way.

Thinkpads are overpriced and except the T series they are specced pretty poorly.

 

[dullard]

So rather than build only your own chips in your fabs, you build other people chips in your fabs and you outsource yours in TSMC since you cant risk having huge capacity if IFS fails and maybe your future nodes aren't very competitive. Also use some of your own capacity for server chips (Xeon) where margins are better.

Intel is now internally two different companies. There is no longer any "own chips" for their fabs. Intel's fab sells its wafers to the highest bidder. Intel's processors are made at the fab on the node that they determine to be right for the job (based on capacity, timing, cost, performance, efficiency, etc. as I outlined above) whether this is Intel Foundry or TSMC or Samsung (for the upcoming Lunar Lake LPDDR5X) or who knows maybe or Global Foundries will be included at some point.

Intel foundry will even produce chips for CPU competitors: ARM, Qualcomm, or AMD if they so choose.

Intel Provides Update on Internal Foundry Model

New model represents fundamental change to operations aimed at unlocking significant value.

www.intel.com

Intel’s manufacturing groups will face the same market dynamics as their external foundry counterparts and need to compete for volume through performance and price. This includes Intel’s internal customers, who will have the flexibility over time to engage with third-party foundries. It’s not an entirely new notion for Intel, however; today, roughly 20% of Intel’s silicon is manufactured externally.

 

[Tigerick]

y

Can you update your post to include this link? http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...akes-discussion-threads.2606448/post-41187952

Would be helpful for new readers.

Yeah, done...Let's hope news reporter don't pick up the changes

 

[Aapje]

Intel is now internally two different companies. There is no longer any "own chips" for their fabs. [etc etc]

You are confusing their goal with where they are right now. Even according to themselves they are still working towards being able to supply chips for more use cases, having tooling that is on par with TSMC and being competitive on price, performance, etc.

And they definitely will try to make their own chips, because if they don't, their foundry business will die. Not just because they need all that volume, but also because other big companies won't trust Intel Foundry if even Intel Design doesn't use them.

 

[dullard]

You are confusing their goal with where they are right now. Even according to themselves they are still working towards being able to supply chips for more use cases, having tooling that is on par with TSMC and being competitive on price, performance, etc.

And they definitely will try to make their own chips, because if they don't, their foundry business will die. Not just because they need all that volume, but also because other big companies won't trust Intel Foundry if even Intel Design doesn't use them.

Since this is a discussion of the fab for a future product, Nova Lake, I think it is quite appropriate to talk about Intel's future fab goals. Applying where Intel is now for future products seems wrong to me. Especially a product that is 2-ish years away. That is a lifetime in technology.

 

[SiliconFly]

Even leaks said its targeting golden cove ipc.. skymont will be 8 wide

Gracemont's IPC is around (6th gen) Skylake IPC only. And I don't think Skymont is going to double the performance over Gracemont. Even a good IPC uplift should put it in the ballpark of Sunny Cove.

I don't think Skymont is going to come anywhere near Golden Cove's IPC.

 

[SiliconFly]

MTL I think, performance at least as good as RPL mobile.

I think MTL performance is just a tad below RPL actually. Probably due to the tile overhead.

 

[tamz_msc]

View attachment 97017

Gracemont's IPC is around (6th gen) Skylake IPC only. And I don't think Skymont is going to double the performance over Gracemont. Even a good IPC uplift should put it in the ballpark of Sunny Cove.

I don't think Skymont is going to come anywhere near Golden Cove's IPC.

Those graphs show overall performance, not IPC. For the latter, divide the SPECint 2017 score by the fMax of the Gracemont cores in Alder Lake.

Raptor Lake E-cores should be a decent uplift over those in Alder Lake in terms of overall performance because of the fixed ring frequency behaviour, doubled L2 per cluster and increase in fMax.

 

[coercitiv]

I think MTL performance is just a tad below RPL actually. Probably due to the tile overhead.

We have data to prove MTL can provide higher throughput at equal power levels. The loss in ST performance is negligible to end users. The product is better than RPL, it's just not good enough of an upgrade considering the time frame.

However, take this opportunity to reflect on the supposed advantage in packaging technology Intel is supposed to have over AMD. The advantage alone is not enough to justify the use of tile segmentation in mobile, IIRC folks like @Exist50 and @IntelUser2000 talked about this long before the product hit the market. Intel is learning though, and in the future this experience will pay dividends.

 

[SiliconFly]

The product is better than RPL...

It's 100% better than RPL without a doubt (I was just talking abt ST).

Almost everything in MTL is awesome. The tiles, GPU, NPU, new process, SoC, NoC Interconnect, Foveros, etc. Everything is perfect; except RWC.

And tbh, I'm not a big fan of RWC. It let me down. Thank god they're killing it sooner rather than later.

 

[Aapje]

Since this is a discussion of the fab for a future product, Nova Lake, I think it is quite appropriate to talk about Intel's future fab goals. Applying where Intel is now for future products seems wrong to me. Especially a product that is 2-ish years away. That is a lifetime in technology.

Yes, if you use future tense.

When discussing the future, you regularly want to refer to the present and the past, which is a lot easier if you use the correct tense for each.

 

[dullard]

However, take this opportunity to reflect on the supposed advantage in packaging technology Intel is supposed to have over AMD. The advantage alone is not enough to justify the use of tile segmentation in mobile, IIRC folks like @Exist50 and @IntelUser2000 talked about this long before the product hit the market. Intel is learning though, and in the future this experience will pay dividends.

In my view, the packaging technology has the main benefit of giving Intel the ability to swap one chip for another in a new iteration of a CPU. That was basically their selling point for the concept when it was first announced years ago with their Client 2.0 presentation.

But of course, if the main benefit is that the NEXT CPU is easier to make means the first CPU gets few of the benefits and all of the drawbacks.

 

[SiliconFly]

In my view, the packaging technology has the main benefit of giving Intel the ability to swap one chip for another in a new iteration of a CPU. That was basically their selling point for the concept when it was first announced years ago with their Client 2.0 presentation.

But of course, if the main benefit is that the NEXT CPU is easier to make means the first CPU gets few of the benefits and all of the drawbacks.

The most import benefit of tiles is significant reduction in validation times. Allows them to iterate very rapidly.