Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

 

[Doug S]

Anandtech has more info:

TSMC's 1.6nm Technology Announced for Late 2026: A16 with "Super Power Rail" Backside Power

www.anandtech.com

They are reporting that N2P is losing BSPD, so I'm back to thinking A16 is mainly N2P with BSPD (probably with some additional tweaks but nothing major). That leaves A14 as the next full node step after N2.

In the last update TSMC was pretty clear that N2 did not have BSPDN, but it would be made available as an option six months later. That N2+BSPDN was not N2P, it was just N2 with BSPDN.

So this talk about N2P losing BSPDN is confusing. Is there no BSPDN until A16, or is that the first node that makes it standard. Or the first node that has "super power rail" and N2+BSPDN has some lesser form of BSPDN.

If BSPDN is out of N2 entirely, and they keep to this schedule where all the new nodes enter mass production in H2, I can't imagine Apple is too happy. What's the point of cooperating closely with your foundry on process development if the timing is wrong and your competition gets the latest processes before you do?

 

[Hitman928]

In the last update TSMC was pretty clear that N2 did not have BSPDN, but it would be made available as an option six months later. That N2+BSPDN was not N2P, it was just N2 with BSPDN.

So this talk about N2P losing BSPDN is confusing. Is there no BSPDN until A16, or is that the first node that makes it standard. Or the first node that has "super power rail" and N2+BSPDN has some lesser form of BSPDN.

If BSPDN is out of N2 entirely, and they keep to this schedule where all the new nodes enter mass production in H2, I can't imagine Apple is too happy. What's the point of cooperating closely with your foundry on process development if the timing is wrong and your competition gets the latest processes before you do?

Anandtech reported that TSMC's roadmap showed BSPD came with N2P.

TSMC's N2 family will evolve and sometime in 2026, when the company plans to introduce its N2P fabrication technology. N2P that will add backside power rails to N2's Nanosheet GAA transistors.

Maybe they were mistaken, but that's where I was getting it from.

TSMC Outlines 2nm Plans: N2P Brings Backside Power Delivery in 2026, N2X Added To Roadmap

www.anandtech.com

Edit:

Also here:

At its Technology Symposium 2023 the company revealed that backside PDN of its N2P will enable 10% to 12% higher performance by reducing IR droop and improving signaling, as well as reducing the logic area by 10% to 15%. Now, of course, such advantages will be more obvious in high-performance CPUs and GPUs that have dense power delivery network and therefore moving it to the back makes a great sense for them.

Backside PDN is a part of TSMC's N2P fabrication technology that will enter HVM in late 2026 or early 2027.

 

[jpiniero]

A16 is probally just N2+Backside with some extra tweaking.

 

[Goop_reformed]

A16 is probally just N2+Backside with some extra tweaking.

Which emphasizes more on the architectures. Nodes are basically about availability/capacity now.