Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

 

[Doug S]

Anandtech has more info:

TSMC's 1.6nm Technology Announced for Late 2026: A16 with "Super Power Rail" Backside Power

www.anandtech.com

They are reporting that N2P is losing BSPD, so I'm back to thinking A16 is mainly N2P with BSPD (probably with some additional tweaks but nothing major). That leaves A14 as the next full node step after N2.

In the last update TSMC was pretty clear that N2 did not have BSPDN, but it would be made available as an option six months later. That N2+BSPDN was not N2P, it was just N2 with BSPDN.

So this talk about N2P losing BSPDN is confusing. Is there no BSPDN until A16, or is that the first node that makes it standard. Or the first node that has "super power rail" and N2+BSPDN has some lesser form of BSPDN.

If BSPDN is out of N2 entirely, and they keep to this schedule where all the new nodes enter mass production in H2, I can't imagine Apple is too happy. What's the point of cooperating closely with your foundry on process development if the timing is wrong and your competition gets the latest processes before you do?

 

[Hitman928]

In the last update TSMC was pretty clear that N2 did not have BSPDN, but it would be made available as an option six months later. That N2+BSPDN was not N2P, it was just N2 with BSPDN.

So this talk about N2P losing BSPDN is confusing. Is there no BSPDN until A16, or is that the first node that makes it standard. Or the first node that has "super power rail" and N2+BSPDN has some lesser form of BSPDN.

If BSPDN is out of N2 entirely, and they keep to this schedule where all the new nodes enter mass production in H2, I can't imagine Apple is too happy. What's the point of cooperating closely with your foundry on process development if the timing is wrong and your competition gets the latest processes before you do?

Anandtech reported that TSMC's roadmap showed BSPD came with N2P.

TSMC's N2 family will evolve and sometime in 2026, when the company plans to introduce its N2P fabrication technology. N2P that will add backside power rails to N2's Nanosheet GAA transistors.

Maybe they were mistaken, but that's where I was getting it from.

TSMC Outlines 2nm Plans: N2P Brings Backside Power Delivery in 2026, N2X Added To Roadmap

www.anandtech.com

Edit:

Also here:

At its Technology Symposium 2023 the company revealed that backside PDN of its N2P will enable 10% to 12% higher performance by reducing IR droop and improving signaling, as well as reducing the logic area by 10% to 15%. Now, of course, such advantages will be more obvious in high-performance CPUs and GPUs that have dense power delivery network and therefore moving it to the back makes a great sense for them.

Backside PDN is a part of TSMC's N2P fabrication technology that will enter HVM in late 2026 or early 2027.

 

[jpiniero]

A16 is probally just N2+Backside with some extra tweaking.

 

[Goop_reformed]

A16 is probally just N2+Backside with some extra tweaking.

Which emphasizes more on the architectures. Nodes are basically about availability/capacity now.

 

[SiliconFly]

Intel 4 is 0.6 x 4/ (150 x 240) + 0.4 x 32/ (950 x 240) = ~122.8 MTr, Intel 3 is 0.6 x 4/ (150 x 210) + 0.4 x 32/(950 x 210) = ~140.35
Math looks like it checks out? Witeken said 150, maybe I missed a scaling factor, idk.
So why does TSMC scale so much better than Intel from HP to HD?
TSMC N3 this time around is using finflex- and that's where the HD figure of ~215MTr/mm2 comes from (with the 48nm CGP as well IIRC). The 2-1 variant. The HP cells, however, is still being compared to the 3-3 variants, and that's with the relaxed 54nm CPP figure as well.
TSMC N3 HD vs HP ratio this time around is ~1.73. TSMC N5 HD vs HP was 1.48. That is a significant difference.
Ok, so what's wrong using the 1.5x scaling figure for Intel then that N5 enjoys?
Well, the cell height scaling is quite simply worse. TSMC N5 HD cell height is 210nm, which is the exact same as the cell height of Intel 3 HD.
View attachment 97648
TSMC's HP cell height is quite high on the other hand, is:
View attachment 97649
(angstronomics 5nm article)
So what makes Intel 4 HP so dense?
Intel 4's Cell Height is quite low.
View attachment 97650
If you look at this, you see that Intel 4 CPP isn't anything that amazing. It's between N5 and N3, an closer to N5 to boot. However its height is literally lower than even N3, and by a decent amount too.
So why doesn't Intel 3 cell height scale better when lowering the fin count?
Well, who knows. Maybe the track count just can't scale much lower, since Intel 4's HP metal track count is already impressively low (at 5.33 vs 9 for N3 and N5).
View attachment 97660
Maybe N5's fin pitch is larger than Intel 4's, which provides it better scaling as you remove fins. Idk.

Regardless, the numbers are right there. Intel themselves claimed a cell height of 210nm for their HD libs, and N5 HD lib cell height is also 210nm. The only thing that's making Intel 4 denser now is the slightly lower CGP of 51 vs 50nm. And for Mark Bohr's calculation, those 2 numbers are pretty much all that matter *** with some asterisks that are described in angstranomics article.

The only thing that can "save" Intel 3's density now is the shrinking of CGP even lower, which wouldn't be new from Intel (Intel 7 had 60/54 nm CGP variants IIRC) but seeing how it's not listed in the abstract while all the other major points are, I doubt it.

TBH I was also expecting a shrink so it would be more competitive against N3, but who knows ¯\_(ツ)_/¯
I'm always pretty much optimistic for Intel... for the first couple months of the rumor mill

N3E has finflex

Based on that rumor of Intel 18A "high density" cells only being marginally more dense than N5 HD cells, I wonder if that's actually due to them not shrinking cell height/cpp or them just not offering a lower amount of fins until something like 18A-P or 14A. That's my copium at least lol.
But ye I agree, I think intel is laser focused on perf/watt (prob perf/watt specifically for HPC too).


SRF is built on both Intel 3 and Intel 7. Without the breakdown of the transistors in the IO vs Compute tiles, the total transistor count figure isn't that helpful for determining the density of Intel 3 itself.
100B transistors has to be 288, cos with 288, we arrive at 86.5, which makes sense. The real density of these server chips should be way below their theoretical density.
Looking at the real density of small mobile chips and seeing how they lineup against server chips is not the play. It's not the area that's the problem, but the completely different ratios of cores/cache/io, and also the iGPU, which is typically made of pretty dense logic (which can provide a decent boost in numbers).
I'm guessing you saw this chart and decided to try this:
View attachment 97659

We can go ahead and look at an example of this not working for server chips. SPR, on Intel 7, has a density of ~30 Mtr/mm2. What's Intel 7's UHP lib density? ~60MTr/mm2. The ratio there is like 50%. But what if we apply this to GNR since the server to logic density ratio looks to be 1/2? This would mean Intel 3 (using the 288C SRF model) could be estimated to be ~170 MTr.... wait a second....
checks twitter
are you literally not counting the IO tile area... at all? Wth!
So lets pretend that Intel 3 vs Intel 7 IO scaling is 2x. I doubt it's that high, but whatever. Let's cut the area of the IO tiles in half now, add in the 2 compute tiles, an area of ~1397 mm2, 100 billion transistors, gives u a density of ~72, which is roughly half of Intel 3's HD lib density of ~140.

Except all this math is bad, because it's never this simple, and we made way too many assumptions on the way. EMR has a transistor density of ~40 MTr. Does this mean Intel's 7 UHP lib density increased to ~80 MTr/mm2? What about ICL server, with its horrendous transistor density? Mixing in compute and IO tiles too, or just ignoring the IO tiles completely....

I think this exercise was a bit pointless tbh. Way too many assumptions.

Lastly, Intel themselves claim they will have worse transistor density with Intel 3 than TSMC 3nm.
View attachment 97661
If it was just slightly worse, as you are suggesting, then they almost certainly would have done a " - ~" rather than a "-" since they also used "+~" elsewhere. I think that minus over there is doing a lot of heavy lifting. And tbh, I would not be surprised if this is specifically in reference to HP logic cells, and ignoring HD cells, SRAM density, analog, etc etc. I also think it's possible the signs for Intel 14A is a lot more wholistic though, since it also includes "mobile" in the target segment. We will see in a couple months ig.

Just found out what happened; about the confusion caused by witeken saying Intel 4 HP cell height is 240nm & Intel 3 HD cell height being a massive 210nm. And you too mentioned the same. Well, it's not!



It wasn't Intel 3 HD cell height thats 210nm, but Intel 4 + BSPD HP cell height thats 210nm.

This means, Intel 3 HD density isn't a meager 150 MTr/mm2 like you mentioned. It's somewhere between 180 to 210 like I mentioned earlier. N3B is around ~200 (and N3E slightly lower). Intel 3 is very easily gonna be almost on par with N3B. A bit behind, but very close.

 

[Geddagod]

It wasn't Intel 3 HD cell height thats 210nm, but Intel 4 + BSPD HP cell height thats 210nm.

Intel is straight up saying Intel 3 HD is 210nm high.

There is literally no confusion here. Intel 3's HD cells are 210nm high.
Also, that Intel 4 + BSPD is not HP. Idk why you cropped it like the image of Intel 4 with BSPD like that....

It's "HD"- look at the fin count- it's 2-2 vs Intel 4 standard being 3-3. What fin count is exactly HP vs HD depends on node per node, but regardless, Intel 4 with BSPD has a lower fin count than Intel 4 without BSPD.
It would be pretty funny if Intel 3 HD was actually 3-3, but they were forced to call it HD because using too few fins would get it trashy performance, compared to N3 HD cells. I doubt it, but it would be pretty funny.
Whatever the reason is though, Intel 3 HD is 210nm, directly according to Intel themselves. And using their naming scheme, it should be compared to TSMC N3 HD cells.

Also, curious about your thoughts on rumors that Intel 18A's densest libs are only going to be marginally denser than N5 HD lol.

 

[dr1337]

Samsung Foundry Update: 2nm Unveil in June, Second-Gen SF3 3nm Hits Production This Year

www.anandtech.com

Interesting tidbit at the end, Samsung is adding chip stacking to its 4nm finfet process. Seems like demand for stacked silicon only goes up, it'll be cool to see what they do with it.

 

[Ghostsonplanets]

Synopsys and Samsung Electronics Collaborate to Achieve First Production Tapeout of Flagship Mobile CPU with Leading Performance on Samsung Foundry's GAA Process

Synopsys.ai Full Stack AI-Driven EDA Suite with CPU-specific Optimizations Delivers Unparalleled PPA with Highest Frequency and 10% Lower Power for Industry's Latest Mobile CPU with Generative AI...

news.synopsys.com

Synopsys, Inc. (Nasdaq: SNPS) today announced that Samsung Electronics has achieved successful production tapeout for its high-performance mobile SoC design, including flagship CPUs and GPUs, with 300MHz higher performance using Synopsys.ai™ full stack AI-driven EDA suite and a broad portfolio of Synopsys IP on Samsung Foundry's latest Gate-All-Around (GAA) process technologies. This significant achievement underscores the close collaboration between Synopsys and Samsung to deliver exceptional performance, power and area (PPA) for mutual customers, enabling a new generation of chips with generative artificial intelligence (AI) capabilities on Samsung Foundry advanced process nodes.

Using AI driven EDA from Synopsis for GAA design (E2500/Dream?) allowed Samsung to achieve 300MHz higher clock while using 10% less dynamic power and savings weeks of manual effort.

 

[adamge]

Asianometry doesn't sound optimistic regarding Intel's investment in high-NA.

 

[Ghostsonplanets]

Asianometry doesn't sound optimistic regarding Intel's investment in high-NA.

Watched it yesterday. The economic structure and play for High-NA isn’t here. This much isn’t news. There's a reason why TSMC is avoiding High-NA as much as possible.

Intel silver bullet seems to be the reported Directed Self Assembly. If they can pull this off and reduce High-NA investments risks, they'll be able to leapfrog competition somewhat. But it's a risky gamble. Samsung Foundry literally was caught with their pants down trying to be the first on EUV and Gaafet/MCBFET. While TSMC preferred the slow and steady approach, which paid off in the end.

So let's see how this play from Intel Foundry will go.

 

[DrMrLordX]

So let's see how this play from Intel Foundry will go.

Might go over as well as all that cobalt and quad-patterning in early 10nm.

 

[KompuKare]

Watched it yesterday. The economic structure and play for High-NA isn’t here. This much isn’t news. There's a reason why TSMC is avoiding High-NA as much as possible.

Intel silver bullet seems to be the reported Directed Self Assembly. If they can pull this off and reduce High-NA investments risks, they'll be able to leapfrog competition somewhat. But it's a risky gamble. Samsung Foundry literally was caught with their pants down trying to be the first on EUV and Gaafet/MCBFET. While TSMC preferred the slow and steady approach, which paid off in the end.

So let's see how this play from Intel Foundry will go.

Technically risky, but with the huge amount of corporate welfare being handed to Intel... The financial risk is Somebody Else's problem!

 

[Saylick]

Watched it yesterday. The economic structure and play for High-NA isn’t here. This much isn’t news. There's a reason why TSMC is avoiding High-NA as much as possible.

Intel silver bullet seems to be the reported Directed Self Assembly. If they can pull this off and reduce High-NA investments risks, they'll be able to leapfrog competition somewhat. But it's a risky gamble. Samsung Foundry literally was caught with their pants down trying to be the first on EUV and Gaafet/MCBFET. While TSMC preferred the slow and steady approach, which paid off in the end.

So let's see how this play from Intel Foundry will go.

Slow and steady is the only viable option for TAMC given their clientele. Even if Intel were to catch up and beat TSMC on a few metrics, I doubt it would change the landscape all too much simply because clients value consistency of service, i.e. one hit wonder nodes don’t cut it for very demanding customers such as Apple. Those kinds of customers need to be reassured that you can offer them improvements generation after generation because their products depend on it. For this reason, it’s rather ironic that Intel is struggling to find customers for IFS at least partially because of the same reasons that allowed them to be entrenched in the server space to begin with: no one got fired for going with TSMC.

 

[Aapje]

There are customers that more opportunistically switch between suppliers, like Nvidia.

 

[Saylick]

There are customers that more opportunistically switch between suppliers, like Nvidia.

Maybe for products which aren’t critical to their bottom line only for now, i.e. an ARM SoC for Windows on ARM.

 

[maddie]

Maybe for products which aren’t critical to their bottom line only for now, i.e. an ARM SoC for Windows on ARM.

Nvidia as mentioned is definitely one. Pre AI boom, their gaming GPUs fabbed at Samsung was the bulk of both revenue and profits.

 

[Doug S]

Nvidia as mentioned is definitely one. Pre AI boom, their gaming GPUs fabbed at Samsung was the bulk of both revenue and profits.

Pre AI boom Samsung's processes weren't in the complete disarray they've been mired in for the last few years. Pre EUV TSMC seemed to have a small advantage, but that may have been less important to Nvidia than other stuff like capacity or price. Going with Samsung today would appear to be pretty risky as there appears to be little evidence they can deliver in quantity on any of their sub 7nm nodes even at smartphone sizes, let alone reticle size like Nvidia's.

Intel's stated goal of becoming the #2 foundry seems easily achieveable even if they have some major missteps, because the only thing the competition has been able to produce in volume since covid started is press releases.

 

[DrMrLordX]

Intel's stated goal of becoming the #2 foundry seems easily achieveable even if they have some major missteps, because the only thing the competition has been able to produce in volume since covid started is press releases.

3GAP (or whatever they call it now) still could be an okay node, and Samsung should be able to offer it in higher volume than anything Intel will have through 18a.