Question: is consumer Blackwell also going to be a multi-chip solution? If so, that would make it very expensive since the wafer yield will essentially get halved.
To get those specs it would have to be 800mm²; that's effectively +33% over AD102 on basically the same node even if the Blackwell SMs don't use more transistors.Predictions?
GB202 4NP (N4P) 800mm2~ mono
192SM
128MB L2
512bit 28Gb/s 1792GB/s
3ghz real in game boost.
How is two chips a monolith?But it's almost certainly going to be a monolith again.
There's no reason for it to be really cut down.
It's not Is this NVIDIA's first "chiplet" design?How is two chips a monolith?
Are you confusing the just announced server Blackwell with consumer Blackwell? Because he was asking about the latter.How is two chips a monolith?
If the consumer Blackwell is a huge monolith, that's bad for their yields and it will be very expensive and hard to cool as a result.Are you confusing the just announced server Blackwell with consumer Blackwell? Because he was asking about the latter.
Chiplets are cheaper at a given total die size than monolithic. Unfortunately for AMD, price is determined by performance, which cost them equal to or more than they saved on chiplets to price match/beat the equivalently performing Nvidia GPU. However, theoretically a chip like B100 that presents as one GPU may scale well enough that the RDNA3 priciing problem is avoidedQuestion: is consumer Blackwell also going to be a multi-chip solution? If so, that would make it very expensive since the wafer yield will essentially get halved.
4NP is about 30% denser than 4N when comparing B100 to H100.To get those specs it would have to be 800mm²; that's effectively +33% over AD102 on basically the same node even if the Blackwell SMs don't use more transistors.
If your predictions are accurate, it'll be interesting to see how cut down consumer RTX 5090 is.
4NP is about 30% denser than 4N when comparing B100 to H100.
I know about N4P, but I am talking about 4NP. The custom process Nvidia is using and comparing H100 vs B100.Nope, N4P only has 6% higher density vs N5
If they use N4P for consumer Blackwell , they will have to increase the die size to 800mm2 to get any meaningful performance increase over ADA.
I know about N4P, but I am talking about 4NP. The custom process Nvidia is using and comparing H100 vs B100.
Even if the gains are not the process but the design, it would still translate to GB202
The reticle limit is ~850mm, B100 die is not larger than thatB100 seems to be close to 1000mm2 to 1100mm2 in die size (per die).
The reticle limit is ~850mm, B100 die is not larger than that
It's hard to tell from the keynote, but when Jensen was holding up the two it certainly didn't look like B100 was much larger if at all than H100. 30% higher average density than Hopper does seem in the realm of possibility if it's 104B transistors. I'm not photoshop expert, but just measuring the clearest die shot I could find from the keynote had the two die B100 complex as 51mmx33mm using the 11x11 HBM3 as a guide. If my crappy measurements were accurate, that'd be 123.7M/mm².
Hopper's not very dense though, it's 98.3M/mm² while AD102 is 125.4M.mm². B100 being 104B at the same die size as H100 would make it very slightly more dense than AD102. It might be more than a little hopeful to think 4NP GB202 will be +30% over 4N AD102.
It'd be interesting to know how they're counting transistors and the average density of the different areas, especially the new interchip interface. B100 only has 4 memory controllers vs 6 in H100 which might help there.
Yeah, the two tweets really seem like kopite7kimi is just saying B100 is 30% denser than H100, which seems to be likely the case. Even his followup tweet indicates you wouldn't think 4NP is +30% over 4N and he doesn't know 4NP.We need to pump the breaks hard on the whole +30% density line. This doesn't come from NV or TSMC, it's from a twitter leaker who claims it without any source or explanation of how he gets to that number. Most likely, he just did what you did here and compared a rough B100 density calculation to H100 but, as you mention AD102, is just as dense despite it being on the "old" 4N node. What is on the chip (how much cache, IO, memory controllers, libraries used, etc.) and how you count the transistors makes a huge difference in density calculations. NV is not getting a 30% density improvement from the process tweak. Even if they went from an N5 based node to an N4P based node with additional tweaks, you're looking at like 7% max.
We need to pump the breaks hard on the whole +30% density line. This doesn't come from NV or TSMC, it's from a twitter leaker who claims it without any source or explanation of how he gets to that number. Most likely, he just did what you did here and compared a rough B100 density calculation to H100 but, as you mention AD102, is just as dense despite it being on the "old" 4N node. What is on the chip (how much cache, IO, memory controllers, libraries used, etc.) and how you count the transistors makes a huge difference in density calculations. NV is not getting a 30% density improvement from the process tweak. Even if they went from an N5 based node to an N4P based node with additional tweaks, you're looking at like 7% max.
The parts AMD removed are notoriously not scaleable on lower process so you are right imo, this would have reduced the density figures if it were monolithic.I guess one thing about density is this:
So despite N4 being "better" than N5 (although it is not as custom as all that), Navi 31's GCD is far denser.
And tellingly the MCD's are far less dense. So never mind yields, but aside from power having the memory controllers and cache on older nodes is a very big thing. Just a pity that AMD were so conservative with their implementation as a 400mm² plus GCD would have made far more sense to get the halo effect. Certainly seems a far saner strategy to me than insisting that Navi 32 had to be chiplet too.
Any source for 2X cache per die? Can't find itWhat is interesting is Nvidia doubled the cache of B100 per die and added 20% more cores at a similar size so there is still an apreciable improvement, whatever it is
But was the design of the chip too dense to reach the desired clocks?I guess one thing about density is this:
So despite N4 being "better" than N5 (although it is not as custom as all that), Navi 31's GCD is far denser.
And tellingly the MCD's are far less dense. So never mind yields, but aside from power having the memory controllers and cache on older nodes is a very big thing. Just a pity that AMD were so conservative with their implementation as a 400mm² plus GCD would have made far more sense to get the halo effect. Certainly seems a far saner strategy to me than insisting that Navi 32 had to be chiplet too.