Super Frame Gen incoming?
Hope not.
They could increase the FP32 and RT cores per SM instead. It would definitely help the comparison with previous gen Ada at least... but what do you think is more likely?
With presumed lower die sizes on the lower end products... there's only so much room left for whatever it is they want to change.
I don't believe in increasing the execution units per SM compared to outright increase the SM count. I don't think the saved space would be significant, but I can be mistaken.
I think Nvidia will keep the current L2 cache size.
I would like something like this:
AD107->GB107: 30SM(+25%); 3840FP32(+25%); 120TMU(+25%); 40ROP(+25%); 24MB L2(+0%); 96-bit 30gbps GDDR7(+32%); 9GB Vram(+13%)
AD106->GB106: 48SM(+33%); 6144FP32(+33%); 192TMU(+33%); 60ROP(+25%); 32MB L2(+0%); 128-bit 30gbps GDDR7(+67%); 12GB Vram(+50%)
AD104->GB104: 72SM(+20%); 9216FP32(+20%); 288TMU(+20%); 96ROP(+20%); 48MB L2(+0%); 192-bit 30gbps GDDR7(+43%); 18GB Vram(+50%)
AD103->GB103: 108SM(+35%); 13824FP32(+35%); 432TMU(+35%); 144ROP(+29%); 64MB L2(+0%); 256-bit 32gbps GDDR7(+39%); 24GB Vram(+50%)
AD102->GB102: 192SM(+33%); 24576FP32(+33%); 768TMU(+33%); 240ROP(+25%); 96MB L2(+0%); 384-bit 32gbps GDDR7(+52%); 36GB Vram(+50%)
or version 2 with different SM config: 128FP32 -> 192FP32(+50%) and 2x more RT units, so @Mopetar will be happy
AD107->GB107v2: 20SM(-17%); 3840FP32(+25%); 80TMU(-17%); 40ROP(+25%); 24MB L2(+0%); 96-bit 30gbps GDDR7(+32%); 9GB Vram(+13%)
AD106->GB106v2: 32SM(-11%); 6144FP32(+33%); 128TMU(-11%); 60ROP(+25%); 32MB L2(+0%); 128-bit 30gbps GDDR7(+67%); 12GB Vram(+50%)
AD104->GB104v2: 48SM(-20%); 9216FP32(+20%); 192TMU(-20%); 96ROP(+20%); 48MB L2(+0%); 192-bit 30gbps GDDR7(+43%); 18GB Vram(+50%)
AD103->GB103v2: 72SM(-10%); 13824FP32(+35%); 288TMU(-10%); 144ROP(+29%); 64MB L2(+0%); 256-bit 32gbps GDDR7(+39%); 24GB Vram(+50%)
AD102->GB102v2: 128SM(-11%); 24576FP32(+33%); 512TMU(-11%); 240ROP(+25%); 96MB L2(+0%); 384-bit 32gbps GDDR7(+52%); 36GB Vram(+50%)
I think with either of these configs die size should be smaller than Ada predecessor by using N3 process.